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ADC08200 Просмотр технического описания (PDF) - Texas Instruments

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ADC08200 8-Bit, 20 Msps to 200 Msps, Low Power A/D Converter with Internal Sample and-Hold TI
Texas Instruments TI
ADC08200 Datasheet PDF : 27 Pages
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ADC08200
www.ti.com
SNAS136M – APRIL 2001 – REVISED MARCH 2013
Figure 33 shows an example of an input circuit using the LMH6702. Any input amplifier should incorporate some
gain as operational amplifiers exhibit better phase margin and transient response with gains above 2 or 3 than
with unity gain. If an overall gain of less than 3 is required, attenuate the input and operate the amplifier at a
higher gain, as shown in Figure 33.
The RC at the amplifier output filters the clock rate energy that comes out of the analog input due to the input
sampling circuit. The optimum time constant for this circuit depends not only upon the amplifier and ADC, but
also on the circuit layout and board material. A resistor value should be chosen between 18and 47and the
capacitor value chose according to the formula
(5)
The value of "C" in the formula above should include the ADC input capacitance when the clock is high
This will provide optimum SNR performance for Nyquist applications. Best THD performance is realized when the
capacitor and resistor values are both zero, but this would compromise SNR and SINAD performance. Generally,
the capacitor should not be added for undersampling applications.
The circuit of Figure 33 has both gain and offset adjustments. If you eliminate these adjustments normal circuit
tolerances may result in signal clipping unless care is exercised in the worst case analysis of component
tolerances and the input signal excursion is appropriately limited to account for the worst case conditions.
Full scale and offset adjustments may also be made by adjusting VRT and VRB, perhaps with the aid of a pair of
DACs.
+5V
0.1 PF
+3V
10 PF
Choke
+ 10 PF
Signal
Input
Gain
Adjust
12
* 10
240
200
-
LMH6702
+
100
47
0.33 PF
*
*
4.7k
+3V
1k
1k
Offset
Adjust
-5V
0.1 PF
*URXQG FRQQHFWLRQV PDUNHG ZLWK ³*´
should enter the ground plane at a
common point
22
10 pF
0.1 PF
1 4 12
6
VA
VIN
18
0.1 PF
DR VD
7
VIN GND
ADC08200 D7
3
VRT
D6
D5
D4
9 VRM
D3
D2
D1
D0
13
14
15
16
19
20
21
22
10
VRB
17
DR GND
23
PD
CLK
AGND
24
2 5 7 8 11
Figure 33. The input amplifier should incorporate some gain for best performance (see text).
POWER SUPPLY CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A
10 µF tantalum or aluminum electrolytic capacitor should be placed within an inch (2.5 cm) of the A/D power
pins, with a 0.1 µF ceramic chip capacitor placed within one centimeter of the converter's power supply pins.
Leadless chip capacitors are preferred because they have low lead inductance.
Copyright © 2001–2013, Texas Instruments Incorporated
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