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ADC08200 Просмотр технического описания (PDF) - Texas Instruments

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ADC08200 8-Bit, 20 Msps to 200 Msps, Low Power A/D Converter with Internal Sample and-Hold TI
Texas Instruments TI
ADC08200 Datasheet PDF : 27 Pages
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ADC08200
www.ti.com
FUNCTIONAL DESCRIPTION
SNAS136M – APRIL 2001 – REVISED MARCH 2013
The ADC08200 uses a new, unique architecture that achieves over 7 effective bits at input frequencies up to and
beyond 100 MHz.
The analog input signal that is within the voltage range set by VRT and VRB is digitized to eight bits. Input voltages
below VRB will cause the output word to consist of all zeroes. Input voltages above VRT will cause the output word
to consist of all ones.
Incorporating a switched capacitor bandgap, the ADC08200 exhibits a power consumption that is proportional to
frequency, limiting power consumption to what is needed at the clock rate that is used. This and its excellent
performance over a wide range of clock frequencies makes it an ideal choice as a single ADC for many 8-bit
needs.
Data is acquired at the rising edge of the clock and the digital equivalent of that data is available at the digital
outputs 6 clock cycles plus tOD later. The ADC08200 will convert as long as the clock signal is present. The
output coding is straight binary.
The device is in the active state when the Power Down pin (PD) is low. When the PD pin is high, the device is in
the power down mode, where the output pins hold the last conversion before the PD pin went high and the
device consumes just 1.4 mW . Holding the clock input low will further reduce the power consumption in the
power down mode to about 1 mW.
APPLICATIONS INFORMATION
REFERENCE INPUTS
The reference inputs VRT and VRB are the top and bottom of the reference ladder, respectively. Input signals
between these two voltages will be digitized to 8 bits. External voltages applied to the reference input pins should
be within the range specified in the Operating Ratings Table. Any device used to drive the reference pins should
be able to source sufficient current into the VRT pin and sink sufficient current from the VRB pin to maintain the
desired voltages.
+3V
10 PF
Choke
+
10 PF
+ 10 PF
+
10 PF
0.1 PF
1 4 12
0.1 PF 18
0.1 PF
6
VA
+3V
VIN
DR VD
1.5V,
nominal
110
1%
0.1 PF
220
1%
0.1 PF
7
VIN GND
3
V RT
ADC08200
9
10
D7
D6
D5
D4
D3
D2
D1
D0
13
14
15
16
19
20
21
22
VRB
23
PD
AGND
2 5 8 11
DR GND CLK
17 24
Because of the ladder and external resistor tolerances, the reference voltage of this circuit can vary too much for
some applications.
Figure 31. Simple, low component count reference biasing.
Copyright © 2001–2013, Texas Instruments Incorporated
Product Folder Links: ADC08200
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