MC68HC05B32VB View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

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MC68HC05B32VB

High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit

Motorola => Freescale 

3.8

Miscellaneous register

Address bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State

on reset

Miscellaneous

$000C POR(1) INTP INTN INTE SFA SFB SM WDOG(2) ?001 000?

(1) The POR bit is set each time there is a power-on reset.

3

(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.

POR — Power-on reset bit (see Section 9.1)

This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the

user to make a software distinction between a power-on and an external reset. This bit cannot be

set by software and is cleared by writing it to zero.

1 (set) – A power-on reset has occurred.

0 (clear) – No power-on reset has occurred.

INTP, INTN — External interrupt sensitivity options (see Section 9.2)

These two bits allow the user to select which edge the IRQ pin will be sensitive to (see Table 3-3).

Both bits can be written to only while the I-bit is set, and are cleared by power-on or external reset,

thus the device is initialised with negative edge and low level sensitivity.

Table 3-3 IRQ sensitivity

INTP INTN

IRQ sensitivity

0

0 Negative edge and low level sensitive

0

1 Negative edge only

1

0 Positive edge only

1

1 Positive and negative edge sensitive

INTE — External interrupt enable (see Section 9.2)

1 (set) – External interrupt function (IRQ) enabled.

0 (clear) – External interrupt function (IRQ) disabled.

The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,

thus enabling the external interrupt function.

MC68HC05B6

MEMORY AND REGISTERS

MOTOROLA

3-9

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