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MC68HC05B32VB View Datasheet(PDF) - Motorola => Freescale

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MC68HC05B32VB Datasheet PDF : 252 Pages
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2.4
Low power modes
The STOP and WAIT instructions have different effects on the programmable timer, the serial
2
communications interface, the watchdog system, the EEPROM and the A/D converter. These
different effects are described in the following sections.
2.4.1 STOP
The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the
internal oscillator is turned off, halting all internal processing including timer, serial
communications interface and the A/D converter (see flowchart in Figure 2-4). The only way for
the MCU to wake-up from the STOP mode is by receipt of an external interrupt or by the detection
of a reset (logic low on RESET pin or a power-on reset).
During STOP mode, the I-bit in the CCR is cleared to enable external interrupts (see Section
10.1.5). The SM bit is cleared to allow nominal speed operation for the 4064 cycles count while
exiting STOP mode (see Section 2.4.3).
All other registers and memory remain unaltered and all input/output lines remain unchanged.
This continues until an external interrupt (IRQ) or reset is sensed, at which time the internal
oscillator is turned on. The external interrupt or reset causes the program counter to vector to the
corresponding locations ($1FFA, B and $1FFE, F respectively).
When leaving STOP mode, a tPORL internal cycles delay is provided to give the oscillator time to
stabilise before releasing CPU operation. This delay is selectable via a mask option to be either
16 or 4064 cycles. The CPU will resume operation by servicing the interrupt that wakes it up, or
by fetching the reset vector, if reset wakes it up.
Warning: If tPORL is selected to be 16 cycles, it is recommended that an external clock signal is
used to avoid problems with oscillator stability while the device is in STOP mode.
Note:
The stacking corresponding to an eventual interrupt to go out of STOP mode will only
be executed when going out of STOP mode.
The following list summarizes the effect of STOP mode on the individual modules of the
MC68HC05B6.
– The watchdog timer is reset; refer to Section 9.1.4.1
– The EEPROM acts as read-only memory (ROM); refer to Section 3.6
– All SCI activity stopped; refer to Section 6.13
– The timer stops counting; refer to Section 5.6
– The PLM outputs remain at current level; refer to Section 7.2
– The A/D converter is disabled; refer to Section 8.3
– The I-bit in the CCR is cleared
MC68HC05B6
MODES OF OPERATION AND PIN DESCRIPTIONS
MOTOROLA
2-7
 

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