MC14532BFR2 View Datasheet(PDF) - ON Semiconductor
Part Name
Description
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MC14532BFR2 Datasheet PDF : 12 Pages
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MC14532B
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
VDD
Ein
GS
Eout
Q2 Q1 Q0
D7 D6 D5 D4 D3 D2 D1 D0
Ein
Eout
Q2 Q1 Q0
Eout = “1”
WITH Din = “0”
3/4 MC14071B
Q3
Q2
Q1
Q0
Figure 4. Two MC14532B’s Cascaded for 4–Bit Output
VDD
VSS
CLOCK
INPUT
DIGITAL TO ANALOG CONVERSION
The digital eight–bit word to be converted is applied to the
inputs of the MC14512 with the most significant bit at
X7 and the least significant bit at X0. A clock input of up to
2.5 MHz (at VDD = 10 V) is applied to the MC14520B.
A compromise between Ibias for the MC1710 and ∆R
between N and P–channel outputs gives a value of R of
[ 33 k ohms. In order to filter out the switching frequencies,
RC should be about 1.0 ms (if R = 33 k ohms, C 0.03 µF).
The analog 3.0 dB bandwidth would then be dc to 1.0 kHz.
ANALOG TO DIGITAL CONVERSION
VDD
An analog signal is applied to the analog input of the
MC1710. A digital eight–bit word known to represent a dig-
itized level less than the analog input is applied to the
MC14512 as in the D to A conversion. The word is increm-
ented at rates sufficient to allow steady state to be reached
between incrementations (i.e. 3.0 ms). The output of the
MC1710 will change when the digital input represents the
first digitized level above the analog input. This word is the
digital representation of the analog word.
C
E
R
1/2 MC14520B
Q1 Q2 Q3 Q4
C
E
R
1/2 MC14520B
Q1 Q2 Q3 Q4
D0 D1 D2 D3 D4 D5 D6 D7
Ein
Q2 Q1 Q0
DIGITAL INPUT/OUTPUT
8–BIT WORD
TO BE CONVERTED
X7 X6 X5 X4 X3 X2 X1 X0
A
B
MC14512
C
Z
STOP
WORD
INCREMENTATION
MC1710
R
ANALOG
OUTPUT
C
ANALOG
INPUT
Figure 5. Digital to Analog and Analog to Digital Converter
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