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DAC-8841 View Datasheet(PDF) - Analog Devices

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DAC-8841 Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
SIGNAL INPUTS (V,nA, B, C, D, E, F, G, H)
The eight independent inputs have a code dependent input
resistance whose worst case minimum value is specified in the
electrical characteristics table. Use a suitable amplifier capable of
driving this input resistance in parallel with the specified input
capacitance. These reference inputs are designed to receive not
X<
only dc, but ac input voltages. This results from the incorpora
tion of a true bilateral analog switch in the DAC design, see
Figure 19. The DAC switch operation has been designed to op
erate in the break-before-make format to minimize transient
loading of the inputs. The reference input voltage range can op
erate from ground (GND) to 1.5 V. That is, the operating input
voltage range, when VnEpL —0 V, is:
0V< Vjj^X < 1.5 V
(2)
P-CH
E DAC
REGSTEH
2R
MSB
LET GND
O Figure 19. DAC-8841 TrimDAC Equivalent Circuit
(One Channel)
The reference inputs can withstand input voltages up to V^d;
however due to the internal amplifier's gain of two configura
S tion, the output voltage of the circuit reaches its maximum spec
ified value of 3 V when the input voltage equals 1.5 V and
VrefL = 0 V; see Figure 18.
The reference low input VrepL is the bottom end of the DAC
B (see Figture 18). This input is normally tied to ground; however
it can be biased above ground. When VpppL is biased above
ground, its value and that of Vip,X should be chosen in agree
O ment with Equation 3.
—^
kV 5
~ Vod-2V
0
12
3
4
VrepL-Volts
Figure 20. DAC-8841 Input Voltage Operating Boundaries
For example, biasing V^EpL equal to one volt would accept a
1 V p-p ac input signal on This input signal could then be
attenuated or given a gain-of-two depending on the DAC data
setting.
DAC OUTPUTS (VoutA, B, C, D, E, F, G, H)
The eight D/A converter outputs are fiilly buffered by the DAC-
8841s internal amplifier. This amplifier is designed to drive up
to 1 kfl loads in parallel with 200 pF. However in order to min
imize internal device power consumption, it is recommended
whenever possible to use larger values of load resistance. The
amplifier output stage can handle shorts to GND; however, care
should be taken to avoid continuous short circuit operation. See
Figure 16 "DAC output current versus VqutX" graph.
The amplifier output is guaranteed to operate to within 2 V of
Vdd under all load conditions and temperature. Figure 8 shows
typical operation to positive output saturation with a 5 mA load.
The low output impedance of the buffers minimizes crosstalk
between analog input channels. At 100 kHz 70 dB of channel-
to-channel isoladon exists. It is recommended to use good cir
cuit layout practice such as guard traces between analog
channels and power supply bypass capacitors. A 0.01 jaF ce
ramic in parallel with a 1-10 |xF tantulum capacitor provides a
good power supply bypass for most frequencies encountered.
DIGITAL INTERFACING
The four digital input pins (CLK, SDI, LD, PR) of the DAC-
8841 were designed for TTL and 5 V CMOS logic compatibil
VouT ^Voo-2V
(3) ity. The SDO output pin offers good fanout in CMOS logic
Also for the general case the headroom restriction to Vpo for
applications and can easily drive several DAC-8841s.
VjnX and VrefL is given by Equation 4.
The Logic Control Input Truth Table II describes how to shift
V^pL <
- 2y
(4) data into the internal 12-bit serial input register. Note that the
According to the above equations, the DAC-8841 can only be
operated under certain combinations of Vj^X and VrefL. The
shaded area in Figure 20 defines the theoretical allowable ranges
CLK is a positive edge-sensitive input. If mechanical switches
are used for breadboard, product evaluation they should be de-
bounced by a flipflop or other suitable means.
of operation. Note that VrefL can be biased higher than Vj^jX. The required address plus data input format is defined in the
Linearity will vary with the reference voltages and supply condi Serial Input Decode Table I. Note there are 8 address states
tions. If a symmetrical output ac signal is desired, then the sym that result in no operation (NOP) or activity in the DAC-8841
metrical ac input on VinX should be offset to VpEpL. The
when the active high load strobe LD is activated. This NOP can
output signal will then be with respect to VrefL.
be used in cascaded applications where only one DAC out of
several packages needs updating. It takes 12 clocks on the CLK
-9-
 

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