DAC-8841 View Datasheet(PDF) - Analog Devices
Part Name
Description
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DAC-8841 Datasheet PDF : 11 Pages
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DAC-8841
pin to fully load the serial input shift register. Data on the SDI
input pin is subject to the timing diagram (Figure 1) data setup
and data hold time requirements. After the twelfth clock pulse,
the processor needs to activate the LD strobe to have the DAC-
8841 decode the serial register contents and update the target
DAG register with the 8-bit data word. This needs to be done
fC
PAO
PA1
PA2
SDI
*
CLK
before the thirteenth positive clock edge. The timing require
DAC-8a41 #1
ments are in the electrical characteristic table and in the Figure
1 timing diagram. After twelve clock edges data initially loaded
into the shift register at SDI appears at the shift register output
SDO.
SDI OACA^
CLK
There is some digital feedthrough from the digital input pins.
DAC-8841 S2
Operating the clock only when the DAG registers require updat
LD
ing minimizes the effect of the digital feedthrough on the analog
SDO OACH]
signal channels.
Figure 21 shows a three-wire interface for a single DAG-8841
that easily cascades for multiple packages.
SDI DACA^
CLK
DAC-8841 #3
E Figure 21. Three-Wire Interface
T DAC-8841 ORDERISNG INFORMATION
Model
DAG8841FP
E DAG8841FW
DAG8841FS
DAG8841GBG
Temperature Range
1
-40°G to +85''G
-40''G to +85°G
+85''G
-40''G to +85''G
Package
Plastic DIP
Gerdip
SOIG
Dice
L For devices processed in total compliance to MIL-STD 883, contact
your localsalesofiSce for the DAC8841BW/883 data sheet.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
O24-Pm Epoxy Dip
0.3" Wide
C'Skinny DIP")
S n n n n n n n n n n n n
0.280(7.11)
B 0.240 (6.10)
Ou u u u u u u u u u u u
0.325 (8.25)
1.275(32.3)
0.300 (7.62)
1.125(28.6)
0.210 (5.33)
MAX
^ MIN 0.015 (0.38)
0.160(4.06) "
0.115(2.92)
0.022 (0.558)
0.014(0.356)
0.100 (2.54) BOS
0.070 (1.77)
0.045 (1.15)
VV
•V k 0.130 (3.30)
MIN
0*-15*
-4r-
0.015 (0.381)
0.008 (0.203)
-10-
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