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ADC0816CCV View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
ADC0816CCV 8-Bit P Compatible A/D Converters with 16-Channel Multiplexer National-Semiconductor
National ->Texas Instruments National-Semiconductor
ADC0816CCV Datasheet PDF : 14 Pages
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Electrical Characteristics (Continued)
Digital Levels and DC Specifications: ADC0816CCN, ADC0817CCN — 4.75VVCC5.25V, −40˚CTA+85˚C unless other-
wise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CONTROL INPUTS
VIN(1)
VIN(0)
IIN(1)
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
(The Control Inputs)
VIN=15V
VCC−1.5
V
1.5
V
1.0
µA
IIN(0)
Logical “0” Input Current
VIN=0
−1.0
µA
(The Control Inputs)
ICC
Supply Current
DATA OUTPUTS AND EOC (INTERRUPT)
fCLK=640 kHz
0.3
3.0
mA
VOUT(1)
VOUT(0)
VOUT(0)
IOUT
Logical “1” Output Voltage
Logical “0” Output Voltage
Logical “0” Output Voltage EOC
TRI-STATE Output Current
IO=−360 µA, TA=85˚C
IO=−300 µA, TA=125˚C
IO=1.6 mA
IO=1.2 mA
VO=VCC
VO=0
VCC−0.4
−3.0
V
0.45
V
0.45
V
3.0
µA
µA
Electrical Characteristics
Timing Specifications: VCC=VREF(+)=5V, VREF(−)=GND, tr=tf=20 ns and TA=25˚C unless otherwise noted.
Symbol
Parameter
Conditions
Min Typ
Max
tWS
tWALE
ts
TH
tD
Minimum Start Pulse Width
Minimum ALE Pulse Width
Minimum Address Set-Up Time
Minimum Address Hold Time
Analog MUX Delay Time
from ALE
(Figure 5) (Note 7)
(Figure 5)
(Figure 5)
(Figure 5)
RS=O(Figure 5)
100
200
100
200
25
50
25
50
1
2.5
tH1, tH0
t1H, t0H
tC
fc
tEOC
OE Control to Q Logic State
OE Control to Hi-Z
Conversion Time
Clock Frequency
EOC Delay Time
CL=50 pF, RL=10k (Figure 8)
CL=10 pF, RL=10k (Figure 8)
fc=640 kHz, (Figure 5) (Note 8)
(Figure 5)
125
250
125
250
90
100
116
10
640
1280
0
8+2µs
CIN
COUT
Input Capacitance
TRI-STATE Output
Capacitance
At Control Inputs
At TRI-STATE Outputs (Note 8)
10
15
10
15
Units
ns
ns
ns
ns
µs
ns
ns
µs
kHz
Clock
Periods
pF
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: A zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC.
Note 4: Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop
greater than the VCC supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage
by more than 100 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage
of 4.900 VDC over temperature variations, initial tolerance and loading.
Note 5: Total unadjusted error includes offset, full-scale, and linearity errors. See Figure 3. None of these A/Ds requires a zero or full-scale adjust. However, if an
all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference voltages can be
adjusted to achieve this. See Figure 13.
Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has
little temperature dependence (Figure 6). See paragraph 4.0.
Note 7: If start pulse is asynchronous with converter clock or if fc > 640 kHz, the minimum start pulse width is 8 clock periods plus 2 µs. For synchronous operation
at fc 640 kHz take start high within 100 ns of clock going low.
Note 8: The outputs of the data register are updated one clock cycle before the rising edge of EOC.
Note 9: Human body model, 100 pF discharged through a 1.5 kresistor.
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