PD488588 View Datasheet(PDF) - Elpida Memory, Inc

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PD488588

288M bits Direct Rambus DRAM

Elpida Memory, Inc 

µPD488588

RD Command: The RD (read) command causes one of the 128 dualocts of one of the sense amps to be transmitted

on the DQA/DQB pins of the Channel.

WR Command: The WR (write) command causes a dualoct received from the DQA/DQB data pins of the Channel to

be loaded into the write buffer. There is also space in the write buffer for the BC bank address and C column

address information. The data in the write buffer is automatically retired (written with optional bytemask) to one of the

128 dualocts of one of the sense amps during a subsequent COP command. A retire can take place during a RD,

WR, or NOCOP to another device, or during a WR or NOCOP to the same device. The write buffer will not retire

during a RD to the same device. The write buffer reduces the delay needed for the internal DQA/DQB data path turn-

around.

PREC Precharge: The PREC, RDA and WRA commands are similar to NOCOP, RD and WR, except that a precharge

operation is performed at the end of the column operation. These commands provide a second mechanism for

performing precharge.

PREX Precharge: After a RD command, or after a WR command with no byte masking (M=0), a COLX packet may

be used to specify an extended operation (XOP). The most important XOP command is PREX. This command

provides a third mechanism for performing precharge.

Data Sheet E0039N30 (Ver. 3.0)

9

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