PD488588FF-C60-53-DH1 View Datasheet(PDF) - Elpida Memory, Inc

Part Name

Description

View to exact match

PD488588FF-C60-53-DH1

288M bits Direct Rambus DRAM

Elpida Memory, Inc 

µPD488588

1. General Description

The figure on page 5 is a block diagram of the µ PD488588. It consists of two major blocks : a “core” block built from

banks and sense amps similar to those found in other types of DRAM, and a Direct Rambus interface block which

permits an external controller to access this core at up to 1.6 GB/s.

Control Registers: The CMD, SCK, SIO0, and SIO1 pins appear in the upper center of the block diagram. They are

used to write and read a block of control registers. These registers supply the RDRAM configuration information to a

controller and they select the operating modes of the device. The nine bit REFR value is used for tracking the last

refreshed row. Most importantly, the five bits DEVID specifies the device address of the RDRAM on the Channel.

Clocking: The CTM and CTMN pins (Clock-To-Master) generate TCLK (Transmit Clock), the internal clock used to

transmit read data. The CFM and CFMN pins (Clock-From-Master) generate RCLK (Receive Clock), the internal

clock signal used to receive write data and to receive the ROW and COL pins.

DQA, DQB Pins: These 18 pins carry read (Q) and write (D) data across the Channel. They are multiplexed / de-

multiplexed from / to two 72-bit data paths (running at one-eighth the data frequency) inside the RDRAM.

Banks: The 32 Mbyte core of the RDRAM is divided into 32 one-Mbyte banks, each organized as 512 rows, with

each row containing 128 dualocts (2K bytes), and each dualoct containing 16 bytes. A dualoct is the smallest unit of

data that can be addressed.

Sense Amps: The RDRAM contains 34 sense amps. Each sense amp consists of 1,024 bytes of fast storage (512

for DQA and 512 for DQB) and can hold one-half of one row of one bank of the RDRAM. The sense amp may hold

any of the 512 half-rows of an associated bank. However, each sense amp is shared between two adjacent banks of

the RDRAM (except for numbers 0, 15, 30, and 31). This introduces the restriction that adjacent banks may not be

simultaneously accessed.

RQ Pins: These pins carry control and address information. They are broken into two groups. RQ7..RQ5 are also

called ROW2..ROW0, and are used primarily for controlling row accesses. RQ4..RQ0 are also called COL4..COL0,

and are used primarily for controlling column accesses.

ROW Pins: The principle use of these three pins is to manage the transfer of data between the banks and the sense

amps of the RDRAM. These pins are de-multiplexed into a 24-bit ROWA (row-activate) or ROWR (row-operation)

packet.

COL Pins: The principle use of these five pins is to manage the transfer of data between the DQA/DQB pins and the

sense amps of the RDRAM. These pins are de-multiplexed into a 23-bit COLC (column-operation) packet and either

a 17-bit COLM (mask) packet or a 17-bit COLX (extended-operation) packet.

ACT Command: An ACT (activate) command from an ROWA packet causes one of the 512 rows of the selected

bank to be loaded to its associated sense amps (two 512 byte sense amps for DQA and two for DQB).

PRER Command: A PRER (precharge) command from an ROWR packet causes the selected bank to release its

two associated sense amps, permitting a different row in that bank to be activated, or permitting adjacent banks to be

activated.

8

Data Sheet E0039N30 (Ver. 3.0)

Share Link: