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PD488588FF-C60-53-DH1 View Datasheet(PDF) - Elpida Memory, Inc

Part Name
Description
View to exact match
PD488588FF-C60-53-DH1
Elpida
Elpida Memory, Inc Elpida
PD488588FF-C60-53-DH1 Datasheet PDF : 79 Pages
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ยตPD488588
Pin Description
Signal
Input / Output Type #pins
Description
SIO0, SIO1
CMD
SCK
Input / Output CMOS Note1 2
Input
CMOS Note1
1
Input
CMOS Note1
1
Serial input/output. Pins for reading from and writing to the control registers using
a serial access protocol. Also used for power management.
Command input. Pins used in conjunction with SIO0 and SIO1 for reading from
and writing to the control registers. Also used for power management.
Serial clock input. Clock source used for reading from and writing to the control
registers.
VDD
18 Supply voltage for the RDRAM core and interface logic.
VDDa
1 Supply voltage for the RDRAM analog circuitry.
VCMOS
2 Supply voltage for CMOS input/output pins.
GND
22 Ground reference for RDRAM core and interface.
GNDa
2 Ground reference for RDRAM analog circuitry.
DQA8..DQA0 Input / Output RSL Note2
CFM
Input
RSL Note2
CFMN
Input
RSL Note2
9 Data byte A. Nine pins which carry a byte of read or write data between the
Channel and the RDRAM.
1 Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
1 Clock from master. Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
VREF
CTMN
Input
RSL Note2
CTM
Input
RSL Note2
ROW2..ROW0
Input
RSL Note2
COL4..COL0
Input
RSL Note2
DQB8..DQB0 Input / Output RSL Note2
1 Logic threshold reference voltage for RSL signals.
1 Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Negative polarity.
1 Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Positive polarity.
3 Row access control. Three pins containing control and address information for
row accesses.
5 Column access control. Five pins containing control and address information for
column accesses.
9 Data byte B. Nine pins which carry a byte of read or write data between the
Channel and the RDRAM.
Total pin count per package
80
Notes 1. All CMOS signals are high-true ; a high voltage is a logic one and a low voltage is logic zero.
2. All RSL signals are low-true ; a low voltage is a logic one and a high voltage is logic zero.
4
Data Sheet E0039N30 (Ver. 3.0)
 

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