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EF6805U3FND View Datasheet(PDF) - STMicroelectronics

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STMicroelectronics ST-Microelectronics
EF6805U3FND Datasheet PDF : 31 Pages
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Half Carry (H) - Set during ADD and ADC operations
to indicate that a carry occurred between bits 3 and
Interrupt (I) - When this bit is set, the timer an exter-
nal interrupts (INT and INT2) are masked (disabled).
If an interrupt occurs while this bit is set, the interrupt
is latched and is processed as soon as the interrupt
bit is cleared.
Negative (N) - When set, this bit indicates that the
result of the last arithmetic, logical, or data manipu-
lation was negative (bit 7 in the result is a logical "1").
Zero (Z) - When set, this bit indicates that the result
of the last arithmetic, logical, or data manipulation
was zero.
Carry/Borrow (C) - When set, this bit indicates that
a carry or borrow ou of the Arithmetic Logic Unit
(ALU) occurred during the last arithmetic operation.
This bit is also affected during bit test and branch in-
structions plus shifts and rotates.
The timer circuitry for the EF6805U3 is shown in fig-
ure 10. The timer contains a single 8-bit software
programmable counter with a 7-bit software selec-
table prescaler. The counter may be preset under
program control and decrements toward zero.
When the counter decrements to zero, the timer in-
terrupt request bit, i.e., bit 7 of the timer control re-
gister (TCR), is set. Then if the timer interrupt is not
masked, i.e.,bit 6 of the TCR and the I bit in the
condition code register are both cleared, the proces-
sor receives an interrupt. After completion of the cur-
rent instruction, the processor proceeds to store the
appropriate registers on the stack, and then fetches
the timer interrupt vector from locations $FF8 and
$FF9 in order to begin servicing the interrupt.
The counter continues to count after it reaches zero,
allowing the software to determine the number of in-
ternal or external input clocks since the timer inter-
rupt request bit was set. The counter may be read
at any time by the processor without disturbing the
count. The contents of the counter become stable
prior to the read portion of a cycle and do not change
during the read. The timer interrupt request bit re-
mains set until cleared by the software. If a write oc-
curs before the timer interrup is sericed, the interrupt
is lost. TCR7 may also be used as a scanned status
bit in a non-interrupt mode of operation (TCR6 = 1).
The prescaler is a 7-bit divider which is used to ex-
tend the maximum length of the timer. Bit 0, bit 1,
and bit 2 of the TCR are programmed to choose the
appropriate prescaler outptu which is used as the
counter input. The processor cannot writ eijto or
read from the prescaler ; however, its contents are
cleared to all zeros by the write operation into TCR
when bit 3 of the written data equals one, which al-
lows for truncation-free counting.
The timer input can be configured for three different
operating modes, plus a disable mode, depending
on the value written to the TCR4 and TCR5 control
bits. For further information see figure 9.
Timer Input Mode 1 - If TCR5 adn TCR4 are both
programmed to a zero, the inpt to the timer is from
an internal clock and the external TIMER input is di-
sabled. The internal clock mode canbe used for pe-
riodic interrupt generation, as well as a referene in
frequency and event measurement. The internal
clock is the instruction cycle clock.
Timer Input Mode 2 - With TCR5 = 0 and TCR4 =
1, the internal clock and the TIMER input pin are AN-
Ded to form the timer input signal. This mode can be
used to measure external pulse widths. The external
timer input pulse simply turns on the internal clock
for the duration of the pulse widths.
Timer Input Mode 3 - If TCR5 = 1 and TCR4 = 0, then
all inputs to the timer are disabled.
Timer Input Mode 4 - If TCR5 = 1 and TCR4 = 1, the
internal clock input to the timer is disabled and the
TIMER input pin becomes the input to the timer. The
external TIMER pin can, in this mode, be used to
count external events as well as external frequen-
cies for generating periodic interrupts.
TCR7 - Timer Interrupt Request Bit :
7 6 5 4 3 2 10
* Write only (read as zero).
1 - Set when TDR goes to zero, or under pro-
gram control
0 - Cleared on external Reset, Power-On-Re-
set, or under Program Control.
TCR6 - Timer Interrupt Mask Bit :
1 - Timer Interrupt masked (disabled) Set on
external Reset, Power-On-Reset, or under
Program Control
0 - Cleared under Program Control.
TCR5 - External or Internal Clock Source Bit :
1 - External Clock Source. Set on external Re-
set, Power-On-Reset, or under Program
0 - Cleared under Program Control.
TCR4 - External Enable Bit :
1 - Enable external TIMER pin. Set on external
Reset, Poxer-On-Reset, or under Program

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