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EF6805U3FND View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
STMicroelectronics ST-Microelectronics
EF6805U3FND Datasheet PDF : 31 Pages
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self-check is called at location $F6D and returns with
the Z bit cleared if any error was found ; otherwise
Z = 1.
In order to work correctly as a user subroutine, the
internal 2 clock must be the clocking source and in-
terrupts must be disabled. Also, on exit, the clock is
running and the interrupt mask is not set so the caller
must protect from interrupts if necessary.
The A and X register contents are lost. This routine
sets the prescaler for divide-by-128 and the timer
data register is cleared. The X register is configured
to count down the same as the timer data register.
The two registers are then compared every 128 cy-
cles until they both count down to zero. Any mis-
match during the count down is considered as an er-
ror. The A and X registers are cleared on exit from
the routine.
The MCU can be reset three ways : by initial powe-
rup, by the external reset input (RESET) and by an
optional internal low-voltage detect circuit. The RE-
SET input consists mainly of a Schmitt trigger which
senses the RESET line logic level. A typical reset
Schmitt trigger hysteresis curve is shown in figure
12. The Schmitt trigger provides an internal reset
voltage if it senses a logical zero on the RESET pin.
Power-On Reset (POR) - An internal reset is gene-
rated upon powerup that allows the internal clock
generator to stabilize. A delay of tRHL milliseconds
is required before allowing the RESET input to go
high. Refer to the power and reset timing diagram
of figure 13. Connecting a capacitor to the RESET
input (as illustrated in figure 14) typically provides
sufficient delay. During powerup, the Schmitt trigger
switches on (removes reset) when RESET rises to
Figure 12 : Typical Reset Schmitt Trigger Hysteresis.
Figure 13 : Power and Reset Timing.
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