PCA9560 View Datasheet(PDF) - Philips Electronics

Part Name

Description

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PCA9560

Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch

Philips Electronics 

Philips Semiconductors

Dual 5-bit multiplexed 1-bit latched

I2C EEPROM DIP switch

Product data

PCA9560

Acknowledge

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits

is followed by one acknowledge bit. The acknowledge bit is a HIGH-level put on the bus by the transmitter whereas the master generates an

extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an

acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down

the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock

pulse, set-up and hold times must be taken into account.

A receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the

slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

S

not acknowledge

acknowledge

1

2

8

9

START condition

Figure 8. Acknowledgement on the I2C-bus

clock pulse for

acknowledgement

SW00368

2003 Jun 27

8

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