datasheetbank_Logo    Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :

DP83820BVUW-AB View Datasheet(PDF) - National ->Texas Instruments

Part NameDP83820BVUW-AB National-Semiconductor
National ->Texas Instruments National-Semiconductor
Description10/100/1000 Mb/s PCI Ethernet Network Interface Controller
DP83820BVUW-AB Datasheet PDF : 87 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
2.0 Pin Descriptions (Continued)
Media Independent Interface (MII) - and Gigabit Media Independent Interface (GMII).
Symbol
TXD7/MA15,
TXD6/MA14,
TXD5/MA13,
TXD4/MA12,
TXD3/MA11,
TXD2/MA10,
TXD1/MA9,
TXD0/MA8
TXEN/TXD8
TXER/TXD9
GTXCLK/
TXPMACLK
REF125
Pin No(s)
152,
151,
148,
147,
146,
145,
142,
141
153
154
140
137
Direction
O
O
O
O
I
Description
Gigabit Transmit Data: This is a group of 8 signals which are driven
synchronous to GTXCLK. TXD7 is the most significant bit.
Transmit Data: This is a group of 4 data signals which are driven synchronous
to the TXCLK for transmission to the external PMD. TXD3 is the most significant
bit and TXD0 is the least significant bit. TXD7 through TXD4 are not used in this
mode
TBI Transmit Data: In TBI mode, this is the lower 8 bits of the 10-bit TBI
Transmit data.
BIOS ROM Address: During external BIOS ROM access, these signals
become part of the ROM address.
Transmit Enable: This signal is synchronous to TXCLK and provides precise
framing for data carried on TXD3-0 for the external PMD. It is asserted when
TXD3-0 contains valid data to be transmitted.
TBI Transmit Data: In TBI mode, this is TXD8 of the 10-bit TBI Transmit data.
Transmit Error: This signal is synchronous to TXCLK and provides error
indications and also is used for 1000 Mb/s half-duplex carrier extension and
packet bursting functions. The DP83820 will only assert this signal in 1000 Mb/s
mode of operation.
TBI Transmit Data: In TBI mode, this is TXD9 of the 10-bit TBI Transmit data.
GMII transmit Clock: A continuous clock used for 1000 Mb/s. It is output to an
external PMD and is the reference clock for Transmit GMII signaling. The clock
frequency is 125 MHz.
TBI Transmit Clock: In TBI mode, this is the 125MHz transmit clock to an
external PMD and is the reference for Transmit TBI signaling.
125 MHz Reference Clock: May be optionally connected to a 125 MHz
oscillator for 1000 Mb/s mode. If not used should be tied high.
BIOS ROM/Flash Interface
Symbol
MCSN
Pin No(s)
92
MD7, MD6,
MD5, MD4/EEDO,
MD3, MD2,
MD1/CFGDISN,
MD0/PMGDISN
MA15/TXD7,
MA14/TXD6,
MA13/TXD5,
MA12/TXD4,
MA11/TXD3,
MA10/TXD2,
MA9/TXD1,
MA8/TXD0,
MA7, MA6,
MA5, MA4/EECLK,
MA3/EEDI, MA2,
MA1, MA0
104, 103,
102, 101,
98, 97,
96,
95,
152,
151,
148,
147,
146,
145,
142,
141,
114, 113,
112, 109,
108, 107,
106, 105
Direction
O
I/O
Description
BIOS PROM/Flash Chip Select: During a BIOS ROM/Flash access, this
signal is used to select the ROM device.
BIOS ROM/Flash Data Bus: During a BIOS ROM/Flash access these
signals are used to transfer data to or from the ROM/Flash device.
MD5:0 and MD7 pin pads have an internal weak pull up.
MD6 pin pad has an internal weak pull down.
O
BIOS ROM/Flash Address: During a BIOS ROM/Flash access, these
signals are used to drive the ROM/Flash address.
6
www.national.com
Direct download click here
 

General Description
DP83820 is a single-chip 10/100/1000 Mb/s Ethernet Controller for the PCI bus. It is targeted at high
performance adapter cards and mother boards. The DP83820 fully implements the V2.2 66 MHz, 64-bit PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83820 can support full duplex 10/100/1000 Mb/s transmission and reception.

Features
— IEEE 802.3 Compliant, 66/33 Mhz, 64/32-bit PCI V2.2 MAC/BIU supports data rates from 1 Mb/s to 1000 Mb/s. This allows support for traditional 10 Mb/s Ethernet, 100 Mb/s Fast Ethernet, as well as 1000 Mb/s Gigabit Ethernet.
— Flexible, programmable Bus master - burst sizes of up to 256 dwords (1024 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98, PC99, and OnNow, including directed packets, Magic Packet with SecureOn, ARP packets, pattern match packets, and Phy status change
— GMII/MII provides IEEE 802.3 standard interface to support 10/100/1000 Mb/s physical layer devices
— Ten-Bit Interface (TBI) for support of 1000BASE-X
— Virtual LAN (VLAN) and long frame support. VLAN tag insertion support for transmit packets. VLAN tag detection and removal for receive packets
— 802.3x Full duplex flow control, including automatic transmission of Pause frames based on Rx FIFO thresholds
— IPv.4 checksum task off-loading. Supports checksum generation and verification of IP, TCP, and UDP headers
— 802.1D and 802.1Q priority queueing support. Supports multiple priority queues in both transmit and receive directions.
— Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 2,048 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns.
— Statistics gathered for support of RFC 1213 (MIB II), RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing CPU overhead for management.
— Internal 8 KB Transmit and 32 KB Receive data FIFOs
— Supports Jumbo packets
— Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Full Duplex support for 10/100/1000 Mb/s data rates
— 208-pin PQFP package
— Low power CMOS design
— 3.3V powered I/Os with 5V tolerant inputs
— JTAG Boundary Scan supported

Share Link : National-Semiconductor
All Rights Reserved © datasheetbank.com 2014 - 2018 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]