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DP83820BVUW-AB View Datasheet(PDF) - National ->Texas Instruments

Part NameDP83820BVUW-AB National-Semiconductor
National ->Texas Instruments National-Semiconductor
Description10/100/1000 Mb/s PCI Ethernet Network Interface Controller
DP83820BVUW-AB Datasheet PDF : 87 Pages
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4.0 Register Set (Continued)
22-20
19
18-16
15-8
7-0
MXDMA
BRST_DIS
FLTH
DRTH
Max DMA Burst Size per Tx
DMA Burst
1000 Mb/s Burst Disable
Tx Fill Threshold
Tx Drain Threshold
This field sets the maximum size of transmit DMA data bursts according to
the following table:
000 = 256 32-bit words (1024 bytes)
001 = 2 32-bit words (8 bytes)
010 = 4 32-bit words (16 bytes)
011 = 8 32-bit words (32 bytes)
100 = 16 32-bit words (64 bytes)
101 = 32 32-bit words (128 bytes)
110 = 64 32-bit words (256 bytes)
111 = 128 32-bit word (512 bytes)
This bit can disable transmit bursting for 1000 Mb/s half-duplex operation.
The bit will have no affect 10/100 Mb/s or full-duplex modes.
unused
Specifies the fill threshold in units of 32 bytes. When the number of
available bytes in the transmit FIFO reaches this level, the transmit bus
master state machine will be allowed to request the PCI bus for transmit
packet fragment reads. A value of 0 in this field will produce unexpected
results and must not be used.
Specifies the drain threshold in units of 32 bytes. When the number of bytes
in the FIFO reaches this level (or the FIFO contains at least one complete
packet) the MAC transmit state machine will begin the transmission of a
packet. NOTE: In order to prevent a deadlock condition from occurring, the
transmit drain threshold should never be set higher than the (txFIFOsize -
TXCFG:FLTH). A value of 0 in this field will prevent draining of the packet
until the complete packet has been loaded into the FIFO.
4.2.13 General Purpose I/O Control Register
This register allows configuration of the General Purpose I/O pins. Note that these pins are especially useful when
interfacing to a Ten-Bit Interface Phy Device.
Tag: GPIOR
Size: 32 bits
Hard Reset: 00000000h
Offset: 002Ch
Access: Read Write
Soft Reset: 00000000h
bit
31-15
14
13
12
11
10
9
8
7
6
tag
GP5_IN
GP4_IN
GP3_IN
GP2_IN
GP1_IN
GP5_OE
GP4_OE
GP3_OE
GP2_OE
description
usage
unused
General Purpose Pin 5 Input Input value from the GP5 pin. When GP5_OE is a 1, this should reflect the
Value
value of GP5_OUT. RO
General Purpose Pin 4 Input Input value from the GP4 pin. When GP4_OE is a 1, this should reflect the
Value
value of GP4_OUT. RO
General Purpose Pin 3 Input Input value from the GP3 pin. When GP3_OE is a 1, this should reflect the
Value
value of GP3_OUT. RO
General Purpose Pin 2 Input Input value from the GP2 pin. When GP2_OE is a 1, this should reflect the
Value
value of GP2_OUT. RO
General Purpose Pin 1 Input Input value from the GP1 pin. When GP1_OE is a 1, this should reflect the
Value
value of GP1_OUT. RO
General Purpose Pin 5
Output Enable
Enables the GP5 pin for use as an output. This bit is loaded from EEPROM
at power-up. R/W
General Purpose Pin 4
Output Enable
Enables the GP4 pin for use as an output. This bit is loaded from EEPROM
at power-up. R/W
General Purpose Pin 3
Output Enable
Enables the GP3 pin for use as an output. This bit is loaded from EEPROM
at power-up. R/W
General Purpose Pin 2
Output Enable
Enables the GP2 pin for use as an output. This bit is loaded from EEPROM
at power-up. R/W
50
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General Description
DP83820 is a single-chip 10/100/1000 Mb/s Ethernet Controller for the PCI bus. It is targeted at high
performance adapter cards and mother boards. The DP83820 fully implements the V2.2 66 MHz, 64-bit PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83820 can support full duplex 10/100/1000 Mb/s transmission and reception.

Features
— IEEE 802.3 Compliant, 66/33 Mhz, 64/32-bit PCI V2.2 MAC/BIU supports data rates from 1 Mb/s to 1000 Mb/s. This allows support for traditional 10 Mb/s Ethernet, 100 Mb/s Fast Ethernet, as well as 1000 Mb/s Gigabit Ethernet.
— Flexible, programmable Bus master - burst sizes of up to 256 dwords (1024 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98, PC99, and OnNow, including directed packets, Magic Packet with SecureOn, ARP packets, pattern match packets, and Phy status change
— GMII/MII provides IEEE 802.3 standard interface to support 10/100/1000 Mb/s physical layer devices
— Ten-Bit Interface (TBI) for support of 1000BASE-X
— Virtual LAN (VLAN) and long frame support. VLAN tag insertion support for transmit packets. VLAN tag detection and removal for receive packets
— 802.3x Full duplex flow control, including automatic transmission of Pause frames based on Rx FIFO thresholds
— IPv.4 checksum task off-loading. Supports checksum generation and verification of IP, TCP, and UDP headers
— 802.1D and 802.1Q priority queueing support. Supports multiple priority queues in both transmit and receive directions.
— Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 2,048 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns.
— Statistics gathered for support of RFC 1213 (MIB II), RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing CPU overhead for management.
— Internal 8 KB Transmit and 32 KB Receive data FIFOs
— Supports Jumbo packets
— Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Full Duplex support for 10/100/1000 Mb/s data rates
— 208-pin PQFP package
— Low power CMOS design
— 3.3V powered I/Os with 5V tolerant inputs
— JTAG Boundary Scan supported

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