datasheetbank_Logo   Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :   

DP83820BVUW-AB View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
DP83820BVUW-AB 10/100/1000 Mb/s PCI Ethernet Network Interface Controller National-Semiconductor
National ->Texas Instruments National-Semiconductor
DP83820BVUW-AB Datasheet PDF : 87 Pages
First Prev 41 42 43 44 45 46 47 48 49 50 Next Last
4.0 Register Set (Continued)
22-20
19
18-16
15-8
7-0
MXDMA
BRST_DIS
FLTH
DRTH
Max DMA Burst Size per Tx
DMA Burst
1000 Mb/s Burst Disable
Tx Fill Threshold
Tx Drain Threshold
This field sets the maximum size of transmit DMA data bursts according to
the following table:
000 = 256 32-bit words (1024 bytes)
001 = 2 32-bit words (8 bytes)
010 = 4 32-bit words (16 bytes)
011 = 8 32-bit words (32 bytes)
100 = 16 32-bit words (64 bytes)
101 = 32 32-bit words (128 bytes)
110 = 64 32-bit words (256 bytes)
111 = 128 32-bit word (512 bytes)
This bit can disable transmit bursting for 1000 Mb/s half-duplex operation.
The bit will have no affect 10/100 Mb/s or full-duplex modes.
unused
Specifies the fill threshold in units of 32 bytes. When the number of
available bytes in the transmit FIFO reaches this level, the transmit bus
master state machine will be allowed to request the PCI bus for transmit
packet fragment reads. A value of 0 in this field will produce unexpected
results and must not be used.
Specifies the drain threshold in units of 32 bytes. When the number of bytes
in the FIFO reaches this level (or the FIFO contains at least one complete
packet) the MAC transmit state machine will begin the transmission of a
packet. NOTE: In order to prevent a deadlock condition from occurring, the
transmit drain threshold should never be set higher than the (txFIFOsize -
TXCFG:FLTH). A value of 0 in this field will prevent draining of the packet
until the complete packet has been loaded into the FIFO.
4.2.13 General Purpose I/O Control Register
This register allows configuration of the General Purpose I/O pins. Note that these pins are especially useful when
interfacing to a Ten-Bit Interface Phy Device.
Tag: GPIOR
Size: 32 bits
Hard Reset: 00000000h
Offset: 002Ch
Access: Read Write
Soft Reset: 00000000h
bit
31-15
14
13
12
11
10
9
8
7
6
tag
GP5_IN
GP4_IN
GP3_IN
GP2_IN
GP1_IN
GP5_OE
GP4_OE
GP3_OE
GP2_OE
description
usage
unused
General Purpose Pin 5 Input Input value from the GP5 pin. When GP5_OE is a 1, this should reflect the
Value
value of GP5_OUT. RO
General Purpose Pin 4 Input Input value from the GP4 pin. When GP4_OE is a 1, this should reflect the
Value
value of GP4_OUT. RO
General Purpose Pin 3 Input Input value from the GP3 pin. When GP3_OE is a 1, this should reflect the
Value
value of GP3_OUT. RO
General Purpose Pin 2 Input Input value from the GP2 pin. When GP2_OE is a 1, this should reflect the
Value
value of GP2_OUT. RO
General Purpose Pin 1 Input Input value from the GP1 pin. When GP1_OE is a 1, this should reflect the
Value
value of GP1_OUT. RO
General Purpose Pin 5
Output Enable
Enables the GP5 pin for use as an output. This bit is loaded from EEPROM
at power-up. R/W
General Purpose Pin 4
Output Enable
Enables the GP4 pin for use as an output. This bit is loaded from EEPROM
at power-up. R/W
General Purpose Pin 3
Output Enable
Enables the GP3 pin for use as an output. This bit is loaded from EEPROM
at power-up. R/W
General Purpose Pin 2
Output Enable
Enables the GP2 pin for use as an output. This bit is loaded from EEPROM
at power-up. R/W
50
www.national.com
Direct download click here
 

Share Link : National-Semiconductor
All Rights Reserved © datasheetbank.com 2014 - 2019 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]