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DP83820BVUW-AB View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
DP83820BVUW-AB 10/100/1000 Mb/s PCI Ethernet Network Interface Controller National-Semiconductor
National ->Texas Instruments National-Semiconductor
DP83820BVUW-AB Datasheet PDF : 87 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
2.0 Pin Descriptions (Continued)
PCI Interface
Symbol
SERRN
STOPN
TRDYN
PMEN
3VAUX
PWRGOOD
CLKRUNN
AD63-32
CBEN7-4
REQ64N
ACK64N
PAR64
PCIVIO
Pin No(s)
11
9
6
175
86
85
87
44, 45, 47, 48,
49, 50, 52, 53,
54, 55, 57, 58,
59, 61, 62, 63,
64, 65, 67, 68,
69, 70, 72, 73,
74, 75, 77, 78,
79, 81, 82, 83
38, 39, 41, 42
37
35
43
84
Direction
I/O
I/O
I/O
O
I
I
I/O
I/O
Description
System Error: This signal is asserted low by DP83820 during address parity
errors and system errors if enabled.
Stop: This signal is asserted low by the target device to request the master
device to stop the current transaction.
Target Ready: As a target, this signal will be asserted low when the (slave)
device is ready to complete the current data phase transaction. This signal is
used in conjunction with the IRDYN signal. Data transaction takes place at the
rising edge of PCICLK when both IRDYN and TRDYN are asserted low. As a
master, this signal indicates that the target is ready for the data during write
operation and with the data during read operation.
Power Management Event: This signal is asserted low by DP83820 to indicate
that a power management event has occurred.
PCI Aux Voltage Sense: This pin is used to sense the presence of a 3.3v
auxiliary supply in order to define the PME Support available.
This pin pad has an internal weak pull down.
PCI bus power good: Connected to PCI bus 3.3v power, this pin is used to
sense the presence of PCI bus power during the D3 power management state.
This pin pad has an internal weak pull down.
Clockrun: This signal is asserted low by DP83820 to indicate that a Clockrun
Event has occurred.
64-bit Extension Address and Data: Multiplexed address and data bus.
Provides upper address bits during 64-bit DAC command. During data phase,
used for transferring upper 32-bits of a 64-bit data transaction.
I/O
64-bit Extension Bus Command/Byte Enables: During the address phase
these signals define the bus commandfor a 64-bit DAC command. During a
64-bit data phase these pins indicate which byte lanes contain valid data.
CBEN4 applies to byte 4(bits 39-32) and CBEN7 applies to byte 7(bits 63-56).
I/O
Request 64-bit Transfer: The DP83820 will assert this signal low to request a
64-bit transfer of data. This pin is sampled by the DP83820 during reset to
determine if the device is connected to a 64-bit datapath.
I
Acknowledge 64-bit Transfer: The DP83820 will samples this signal on bus
master cycles when it has requested a 64-bit data transfer. If both REQ64N and
ACK64N are asserted, then a 64-bit transfer will be performed. As a target, the
DP83820 only supports 32-bit transfers, so it will never assert ACK64N.
I/O
Parity Upper DWORD: This signal indicates even parity across AD63-32 and
CBEN7-4 including the PAR64 pin. As a master, PAR64 is driven during
address and write data phases. As a target, the DP83820 only supports 32-bit
transfers, so it will not drive PAR64.
I
PCI Bus VIO: This pin should be connected to the VIO pins of the PCI bus. It
provides a direct connection to the ESDPLUS ring for biasing. It may be
connected to 5V if available. It should not be connected to 3.3V unless all
signaling is 3.3V as this will interfere with 5V tolerance. Care should be taken in
connecting this to power supplies when power management functions are
enabled.
4
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