datasheetbank_Logo    Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :

DP83820BVUW-AB View Datasheet(PDF) - National ->Texas Instruments

Part NameDP83820BVUW-AB National-Semiconductor
National ->Texas Instruments National-Semiconductor
Description10/100/1000 Mb/s PCI Ethernet Network Interface Controller
DP83820BVUW-AB Datasheet PDF : 87 Pages
First Prev 41 42 43 44 45 46 47 48 49 50 Next Last
4.0 Register Set (Continued)
4.2.8 Interrupt Enable Register
The Interrupt Enable Register controls the hardware INTR signal.
Tag: IER
Size: 32 bits
Offset: 0018h
Access: Read Write
Hard Reset: 00000000h
Soft Reset: 00000000h
bit
31-1
0
tag
description
usage
unused
IE
Interrupt Enable When set to 1, the hardware INTR signal is enabled. When set to 0, the hardware INTR
signal will be masked, and no interrupts will be generated. The setting of this bit has no
effect on the ISR or IMR. This provides the ability to disable the hardware interrupt to
the host with a single access (eliminating the need for a read-modify-write cycle). The
actual enabling of interrupts can be delayed based on the Interrupt Holdoff Register
defined in the following section.
4.2.9 Interrupt Holdoff Register
The Interrupt Holdoff Register prevents interrupt assertion for a programmed amount of time.
Tag: IHR
Size: 32 bits
Hard Reset: 00000000h
Offset: 001Ch
Access: Read Write
Soft Reset: 00000000h
bit
31-9
8
7-0
tag
IHCTL
IH
description
Interrupt Holdoff
Control
Interrupt Holdoff
usage
unused
If this bit is set, the interrupt holdoff will restart when the first interrupt condition occurs
and interrupts are enabled. When this bit is not set, the interrupt holdoff will start as
soon as the counter is loaded and interrupts are enabled.
This register contains a counter value for use in preventing interrupt assertion for a
programmed amount of time. When the ISR is read, the interrupt holdoff timer is loaded
with this value. It begins to count down to 0 based on the setting of the IHCTL bit. Once
it reaches 0, interrupts will be enabled. The counter value is in units of 100us.
4.2.10 Transmit Descriptor Pointer Register
This register points to the current Transmit Descriptor. If Transmit Priority Queueing is enabled, this becomes the
Descriptor pointer for Priority Queue 0 (lowest priority).
Tag: TXDP
Size: 32 bits
Hard Reset: 00000000h
Offset: 0020h
Access: Read Write
Soft Reset: 00000000h
bit
31-3
2-0
tag
TXDP
description
Transmit Descriptor Pointer
usage
The current value of the transmit descriptor pointer. When the transmit state
machine is idle, software must set TXDP to the address of a completed
transmit descriptor. While the transmit state machine is active, TXDP will
follow the state machine as it advances through a linked list of active
descriptors. If the link field of the current transmit descriptor is NULL
(signifying the end of the list), TXDP will not advance, but will remain on the
current descriptor. Any subsequent writes to the TXE bit of the CR register
will cause the transmit state machine to reread the link field of the current
descriptor to check for new descriptors that may have been appended to
the end of the list. Transmit descriptors must be aligned on an even 64-bit
boundary in host memory (A2-A0 must be 0).
unused
48
www.national.com
Direct download click here
 

General Description
DP83820 is a single-chip 10/100/1000 Mb/s Ethernet Controller for the PCI bus. It is targeted at high
performance adapter cards and mother boards. The DP83820 fully implements the V2.2 66 MHz, 64-bit PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83820 can support full duplex 10/100/1000 Mb/s transmission and reception.

Features
— IEEE 802.3 Compliant, 66/33 Mhz, 64/32-bit PCI V2.2 MAC/BIU supports data rates from 1 Mb/s to 1000 Mb/s. This allows support for traditional 10 Mb/s Ethernet, 100 Mb/s Fast Ethernet, as well as 1000 Mb/s Gigabit Ethernet.
— Flexible, programmable Bus master - burst sizes of up to 256 dwords (1024 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98, PC99, and OnNow, including directed packets, Magic Packet with SecureOn, ARP packets, pattern match packets, and Phy status change
— GMII/MII provides IEEE 802.3 standard interface to support 10/100/1000 Mb/s physical layer devices
— Ten-Bit Interface (TBI) for support of 1000BASE-X
— Virtual LAN (VLAN) and long frame support. VLAN tag insertion support for transmit packets. VLAN tag detection and removal for receive packets
— 802.3x Full duplex flow control, including automatic transmission of Pause frames based on Rx FIFO thresholds
— IPv.4 checksum task off-loading. Supports checksum generation and verification of IP, TCP, and UDP headers
— 802.1D and 802.1Q priority queueing support. Supports multiple priority queues in both transmit and receive directions.
— Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 2,048 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns.
— Statistics gathered for support of RFC 1213 (MIB II), RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing CPU overhead for management.
— Internal 8 KB Transmit and 32 KB Receive data FIFOs
— Supports Jumbo packets
— Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Full Duplex support for 10/100/1000 Mb/s data rates
— 208-pin PQFP package
— Low power CMOS design
— 3.3V powered I/Os with 5V tolerant inputs
— JTAG Boundary Scan supported

Share Link : National-Semiconductor
All Rights Reserved © datasheetbank.com 2014 - 2018 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]