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DP83820BVUW-AB View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
DP83820BVUW-AB 10/100/1000 Mb/s PCI Ethernet Network Interface Controller National-Semiconductor
National ->Texas Instruments National-Semiconductor
DP83820BVUW-AB Datasheet PDF : 87 Pages
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4.0 Register Set (Continued)
4.2.8 Interrupt Enable Register
The Interrupt Enable Register controls the hardware INTR signal.
Tag: IER
Size: 32 bits
Offset: 0018h
Access: Read Write
Hard Reset: 00000000h
Soft Reset: 00000000h
bit
31-1
0
tag
description
usage
unused
IE
Interrupt Enable When set to 1, the hardware INTR signal is enabled. When set to 0, the hardware INTR
signal will be masked, and no interrupts will be generated. The setting of this bit has no
effect on the ISR or IMR. This provides the ability to disable the hardware interrupt to
the host with a single access (eliminating the need for a read-modify-write cycle). The
actual enabling of interrupts can be delayed based on the Interrupt Holdoff Register
defined in the following section.
4.2.9 Interrupt Holdoff Register
The Interrupt Holdoff Register prevents interrupt assertion for a programmed amount of time.
Tag: IHR
Size: 32 bits
Hard Reset: 00000000h
Offset: 001Ch
Access: Read Write
Soft Reset: 00000000h
bit
31-9
8
7-0
tag
IHCTL
IH
description
Interrupt Holdoff
Control
Interrupt Holdoff
usage
unused
If this bit is set, the interrupt holdoff will restart when the first interrupt condition occurs
and interrupts are enabled. When this bit is not set, the interrupt holdoff will start as
soon as the counter is loaded and interrupts are enabled.
This register contains a counter value for use in preventing interrupt assertion for a
programmed amount of time. When the ISR is read, the interrupt holdoff timer is loaded
with this value. It begins to count down to 0 based on the setting of the IHCTL bit. Once
it reaches 0, interrupts will be enabled. The counter value is in units of 100us.
4.2.10 Transmit Descriptor Pointer Register
This register points to the current Transmit Descriptor. If Transmit Priority Queueing is enabled, this becomes the
Descriptor pointer for Priority Queue 0 (lowest priority).
Tag: TXDP
Size: 32 bits
Hard Reset: 00000000h
Offset: 0020h
Access: Read Write
Soft Reset: 00000000h
bit
31-3
2-0
tag
TXDP
description
Transmit Descriptor Pointer
usage
The current value of the transmit descriptor pointer. When the transmit state
machine is idle, software must set TXDP to the address of a completed
transmit descriptor. While the transmit state machine is active, TXDP will
follow the state machine as it advances through a linked list of active
descriptors. If the link field of the current transmit descriptor is NULL
(signifying the end of the list), TXDP will not advance, but will remain on the
current descriptor. Any subsequent writes to the TXE bit of the CR register
will cause the transmit state machine to reread the link field of the current
descriptor to check for new descriptors that may have been appended to
the end of the list. Transmit descriptors must be aligned on an even 64-bit
boundary in host memory (A2-A0 must be 0).
unused
48
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