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DP83820BVUW-AB View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
DP83820BVUW-AB 10/100/1000 Mb/s PCI Ethernet Network Interface Controller National-Semiconductor
National ->Texas Instruments National-Semiconductor
DP83820BVUW-AB Datasheet PDF : 87 Pages
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4.0 Register Set (Continued)
26
RXDESC3 Rx Descriptor for Priority
Queue 3
25
RXDESC2 Rx Descriptor for Priority
Queue 2
24
RXDESC1 Rx Descriptor for Priority
Queue 1
23
RXDESC0 Rx Descriptor for Priority
Queue 0
22
TXRCMP Transmit Reset Complete
21
RXRCMP Receive Reset Complete
20
DPERR Detected Parity Error
19
SSERR Signaled System Error
18
RMABT Received Master Abort
17
RTABT Received Target Abort
16
RXSOVR Rx Status FIFO Overrun
15
HIBINT High Bits Interrupt Set
14
PHY
Phy interrupt
13
PME
Power Management Event
12
SWI
Software Interrupt
11
MIB
MIB Service
10
TXURN Tx Underrun
9
TXIDLE Tx Idle
8
TXERR Tx Packet Error
7
TXDESC Tx Descriptor
6
TXOK Tx Packet OK
5
RXORN Rx Overrun
4
RXIDLE Rx Idle
3
RXEARLY Rx Early Threshold
2
RXERR Rx Packet Error
1
RXDESC Rx Descriptor
0
RXOK Rx OK
This event is signaled after a receive descriptor with the INTR bit set in the
CMDSTS field has been updated.
This event is signaled after a receive descriptor with the INTR bit set in the
CMDSTS field has been updated.
This event is signaled after a receive descriptor with the INTR bit set in the
CMDSTS field has been updated.
This event is signaled after a receive descriptor with the INTR bit set in the
CMDSTS field has been updated.
Indicates that a requested transmit reset operation is complete.
Indicates that a requested receive reset operation is complete.
This bit is set whenever CFGCS:DPERR is set, but cleared (like all other
ISR bits) when the ISR register is read.
The DP83820 signaled a system error on the PCI bus.
The DP83820 received a master abort generated as a result of target not
responding.
The DP83820 received a target abort on the PCI bus.
Set when an overrun condition occurs on the Rx Status FIFO.
A logical OR of bits 22-16
Set to 1 when interrupt is generated due to change in phy status.
Set when WOL conditioned detected
Set whenever the SWI bit in the CR register is set.
Set when one of the enabled management statistics has reached its
interrupt threshold.
Set when a transmit data FIFO underrun condition occurs.
This event is signaled when the transmit state machine enters the idle state
from a non-idle state. This will happen whenever the state machine
encounters an "end-of-list" condition (NULL link field or a descriptor with
OWN clear).
This event is signaled after the last transmit descriptor in a failed
transmission attempt has been updated with valid status.
This event is signaled after a transmit descriptor with the INTR bit set in the
CMDSTS field has been updated. If priority queueing is enabled, this bit will
be set when any of the TXDESC0-3 bits are set.
This event is signaled after the last transmit descriptor in a successful
transmission attempt has been updated with valid status
Set when a receive data FIFO overrun condition occurs.
This event is signaled when the receive state machine enters the idle state
from a running state. This will happen whenever the state machine
encounters an "end-of-list" condition (NULL link field or a descriptor with
OWN set).
Indicates that the initial Rx Drain Threshold has been met by the incoming
packet, and the transfer of the number of bytes specified by the DRTH field
in the RXCFG register has been completed by the receive DMA engine.
This interrupt condition will occur only once per packet.
This event is signaled after the last receive descriptor in a failed packet
reception has been updated with valid status.
This event is signaled after a receive descriptor with the INTR bit set in the
CMDSTS field has been updated. If priority queueing is enabled, this bit will
be set when any of the RXDESC0-3 bits are set.
Set by the receive state machine following the update of the last receive
descriptor in a good packet.
46
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