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DP83820BVUW-AB View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
DP83820BVUW-AB 10/100/1000 Mb/s PCI Ethernet Network Interface Controller National-Semiconductor
National ->Texas Instruments National-Semiconductor
DP83820BVUW-AB Datasheet PDF : 87 Pages
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4.0 Register Set (Continued)
4.2.5 PCI Test Control Register
Tag: PTSCR
Offset: 000Ch
Size: 32 bits
Access: Read Write
Hard Reset: 00000000h
Soft Reset: 00000000h
bit
31-16
15
14
13
12-11
10
9
8
7
6
5
4
3
2
1
0
tag
RBIST_RST
RBIST_EN
RBIST_DONE
RBIST_RX1FAIL
description
Reserved
Reserved
Reserved
SRAM BIST Reset
Reserved
SRAM BIST Enable
SRAM BIST Done
RX Status FIFO BIST Fail
RBIST_RX0FAIL RX Data FIFO BIST Fail
Reserved
RBIST_TX0FAIL TX Data FIFO BIST Fail
RBIST_HFFAIL Hash Filter BIST Fail
RBIST_RXFAIL RX Filter BIST Fail
EELOAD_EN Enable EEPROM Load
EEBIST_EN Enable EEPROM BIST
EEBIST_FAIL EE BIST Fail indication
usage
Reserved
Reserved. Must be written as a 0.
Reserved
Setting this bit to 1 allows the SRAM BIST engine to be reset. R/W
Reserved
Setting this bit to 1 starts the SRAM BIST engine. R/W
This bit is set to 1 when the SRAM BIST completes each section. RO
This bit is set to 1 if the SRAM BIST detects a failure in RX Status
FIFO SRAM. This bit is cleared only by resetting the BIST. RO
This bit is set to 1 if the SRAM BIST detects a failure in RX Data FIFO
SRAM. This bit is cleared only by resetting the BIST. RO
Reserved
This bit is set to 1 if the SRAM BIST detects a failure in TX Data FIFO
SRAM. This bit is cleared only by resetting the BIST. RO
This bit is set to 1 if the SRAM BIST detects a failure in the hash filter
SRAM. This bit is cleared only by resetting the BIST. RO
This bit is set to 1 if the SRAM BIST detects a failure in the RX filter
SRAM. This bit is cleared only by resetting the BIST. RO
This bit is set to a 1 to manually initiate a load of configuration
information from EEPROM. A 1 is returned while the configuration
load from EEPROM is active. R/W
This bit is set to a 1 to initiate EEPROM BIST, which verifies the
EEPROM data and checksum without reloading configuration values
to the device. A 1 is returned while the EEPROM BIST is active. R/W
This bit is set to a 1 upon completion of the EEPROM BIST
(EEBIST_EN returns 0) if the BIST logic encountered an invalid
checksum. RO
4.2.6 Interrupt Status Register
This register indicates the source of an interrupt when the INTA pin goes active. Enabling the corresponding bits in the
Interrupt Mask Register (IMR) allows bits in this register to produce an interrupt. When an interrupt is active, one or more
bits in this register are set to a 1. The Interrupt Status Register reflects all current pending interrupts, regardless of the
state of the corresponding mask bit in the IMR. Reading the ISR clears all interrupts. Writing to the ISR has no effect.
Tag: ISR
Size: 32 bits
Hard Reset: 00608000h
Offset: 0010h
Access: Read Only
Soft Reset: 00608000h
bit
tag
description
usage
31
Reserved
Reserved
30
TXDESC3 Tx Descriptor for Priority
This event is signaled after a transmit descriptor with the INTR bit set in the
Queue 3
CMDSTS field has been updated.
29
TXDESC2 Tx Descriptor for Priority
This event is signaled after a transmit descriptor with the INTR bit set in the
Queue 2
CMDSTS field has been updated.
28
TXDESC1 Tx Descriptor for Priority
This event is signaled after a transmit descriptor with the INTR bit set in the
Queue 1
CMDSTS field has been updated.
27
TXDESC0 Tx Descriptor for Priority
This event is signaled after a transmit descriptor with the INTR bit set in the
Queue 0
CMDSTS field has been updated.
45
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