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DP83820BVUW-AB View Datasheet(PDF) - National ->Texas Instruments

Part NameDP83820BVUW-AB National-Semiconductor
National ->Texas Instruments National-Semiconductor
Description10/100/1000 Mb/s PCI Ethernet Network Interface Controller
DP83820BVUW-AB Datasheet PDF : 87 Pages
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4.0 Register Set (Continued)
16
MRM_DIS Memory Read Multiple
Disable
This bit can be used to prevent the DP83820 from using the Memory Read
Multiple and Memory Read Line commands. This bit is loaded from
EEPROM at power-up. R/W
15
MWI_DIS Memory Write and Invalidate This bit can be used to prevent the DP83820 from using the MWI
Disable
command. This allows additional control for driver software which may not
have access to the MWIEN bit in Configuration space. This bit is loaded
from EEPROM at power-up. R/W
14
T64ADDR Target 64-bit Addressing
This read-only bit indicates the device will accept 64-bit addressing as a
Enable
target. This bit is loaded from EEPROM at power-up. RO
13
PCI64_DET PCI 64-bit Bus Detected
This status bit indicates the PCI bus was detected to be 64-bit at reset time.
RO
12
DATA64_EN 64-bit Data Enable
Software can use this bit to enable 64-bit data transfers by the Transmit and
Receive DMA engines. If 0, all bus master transfers will be 32-bit. This bit is
loaded from EEPROM at power-up. This bit should be cleared by software if
the PCI bus was not detected as 64-bit capable (PCI_64_DET = 0). R/W
11
M64ADDR Master 64-bit Addressing
Software can set this bit to enable the DMA controllers to use 64-bit
Enable
addressing. When set, the link and bufptr fields in the Descriptors are
assumed to be 64-bit fields. This bit does not affect the device operation as
a target. This bit is loaded from EEPROM at power-up. R/W
10
PHY_RST Reset Phy
Asserts reset to phy using the PHYRST_N pin. R/W
9
PHY_DIS Disable Phy
Setting this bit can be used to disable an external phy by deasserting the
RXEN pin. This can be used to cause a phy to tri-state its RX MII/GMII pins.
R/W
8
EXTSTS_EN Extended Status Enable
When set, the Extended Status field is enabled for Transmit and Receive
Descriptors. This field contains data for supporting the VLAN and IP
Checksum processing features. R/W
7
REQALG PCI Bus Request Algorithm Selects mode for making requests for the PCI bus. When set to 0 (default),
DP83820 will use an aggressive Request scheme. When set to a 1
DP83820 will use a more conservative scheme. R/W
6
SB
Single Back-off
Setting this bit to 1, forces the transmitter back-off state machine to always
back-off for a single 802.3 interframe gap time, instead of following the
802.3 random back-off algorithm. A 0 (default) allows normal transmitter
back-off operation. R/W
5
POW Program Out of Window
This bit controls when the Out of Window collision timer begins counting its
Timer
512 bit slot time. A 0 causes the timer to start after the SFD is received. A 1
causes the timer to start after the first bit of the preamble is received. R/W
4
EXD
Excessive Deferral Abort
Setting this bit to 1 will cause the transmitter to abort transmission on an
excessive deferral. R/W
3
PESEL Parity Error Detection Action This bit controls the assertion of SERR when a data parity error is detected
while the DP83820 is acting as the bus master. When set, parity errors will
not result in the assertion of SERR. When reset, parity errors will result in
the assertion of SERR, indicating a system error. This bit should be set to a
1 by software if the driver can handle recovery from and reporting of data
parity errors. R/W
2
BROM_DIS Disable Boot ROM interface When set to 1, this bit inhibits the operation of the Boot ROM interface logic.
R/W
1
EXT_125 External 125MHz reference When set to a 1, the 125MHz transmit clock for 1000 Mb/s mode is sourced
Select
from the REF125 pin. When set to a 0, the clock is sourced by the internal
clock generator. This bit is loaded from EEPROM at power-up. R/W
0
BEM
Big Endian Mode
When set, DP83820 will perform bus-mastered data transfers in big
endianmode. Note that access to register space is unaffected by the
setting of this bit. R/W
42
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General Description
DP83820 is a single-chip 10/100/1000 Mb/s Ethernet Controller for the PCI bus. It is targeted at high
performance adapter cards and mother boards. The DP83820 fully implements the V2.2 66 MHz, 64-bit PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83820 can support full duplex 10/100/1000 Mb/s transmission and reception.

Features
— IEEE 802.3 Compliant, 66/33 Mhz, 64/32-bit PCI V2.2 MAC/BIU supports data rates from 1 Mb/s to 1000 Mb/s. This allows support for traditional 10 Mb/s Ethernet, 100 Mb/s Fast Ethernet, as well as 1000 Mb/s Gigabit Ethernet.
— Flexible, programmable Bus master - burst sizes of up to 256 dwords (1024 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98, PC99, and OnNow, including directed packets, Magic Packet with SecureOn, ARP packets, pattern match packets, and Phy status change
— GMII/MII provides IEEE 802.3 standard interface to support 10/100/1000 Mb/s physical layer devices
— Ten-Bit Interface (TBI) for support of 1000BASE-X
— Virtual LAN (VLAN) and long frame support. VLAN tag insertion support for transmit packets. VLAN tag detection and removal for receive packets
— 802.3x Full duplex flow control, including automatic transmission of Pause frames based on Rx FIFO thresholds
— IPv.4 checksum task off-loading. Supports checksum generation and verification of IP, TCP, and UDP headers
— 802.1D and 802.1Q priority queueing support. Supports multiple priority queues in both transmit and receive directions.
— Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 2,048 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns.
— Statistics gathered for support of RFC 1213 (MIB II), RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing CPU overhead for management.
— Internal 8 KB Transmit and 32 KB Receive data FIFOs
— Supports Jumbo packets
— Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Full Duplex support for 10/100/1000 Mb/s data rates
— 208-pin PQFP package
— Low power CMOS design
— 3.3V powered I/Os with 5V tolerant inputs
— JTAG Boundary Scan supported

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