datasheetbank_Logo    Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :

DP83820BVUW-AB View Datasheet(PDF) - National ->Texas Instruments

Part NameDP83820BVUW-AB National-Semiconductor
National ->Texas Instruments National-Semiconductor
Description10/100/1000 Mb/s PCI Ethernet Network Interface Controller
DP83820BVUW-AB Datasheet PDF : 87 Pages
First Prev 31 32 33 34 35 36 37 38 39 40 Next Last
4.0 Register Set (Continued)
CCh
CCSR Clockrun Control/Status Register
R/W
D0-DCh
Reserved
E0h
TBICR TBI Control Register
R/W
E4h
TBISR TBI Status Register
R/W
E8h
TANAR TBI Auto-Negotiation Advertisement Register
R/W
ECh
TANLPAR TBI Auto-Negotiation Link Partner Ability Register
R/W
F0h
TANER TBI Auto-Negotiation Expansion Register
R/W
F4h
TESR TBI Extended Status Register
R/W
F8-FCh
Reserved
100-1FCh
Alias of 00-FCh (memory mapped only)
R/W
200-2FC Config. 32-bit Read access of PCI Configuration Registers (memory mapped only)
RO
Registers
300-3FC
Alias of 200-2FC. 32-bit Read access of PCI Configuration Registers (memory
RO
mapped only)
4.2.1 Command Register
This register is used for issuing commands to the DP83820. These commands are issued by setting the corresponding
bits for the function. A global software reset along with individual reset and enable/disable for transmitter and receiver are
provided here. Setting control bits to 0 has no effect, therefore there is no need for Read/modify/writes to this register.
Tag: CR
Size: 32 bits
Hard Reset: 00000000h
Offset: 0000h
Access: Read Write
Soft Reset: 00000000h
bit
31-17
16-13
12-9
8
7
6
5
tag
description
RXPRI RX Priority Queue Select
TXPRI TX Priority Queue Select
RST
Reset
SWI
Software Interrupt
RXR
Receiver Reset
usage
unused
If Receive Priority Queueing is enabled, these bits indicate which queues
should be enabled or disabled if the RXE or RXD bits are set during a write
to this register. Bit 16 corresponds to Priority Queue 3 (highest priority),
while bit 13 corresponds to Priority Queue 0 (lowest priority). Multiple
queues can be enabled or disabled on a single access. If Priority Queueing
is disabled, then these bits have no effect. These bits read back the
enabled status for the RX Priority Queues.
If Transmit Priority Queueing is enabled, these bits indicate which queues
should be enabled or disabled if the TXE or TXD bits are set during a write
to this register. Bit 12 corresponds to Priority Queue 3 (highest priority),
while bit 9 corresponds to Priority Queue 0 (lowest priority). Multiple
queues can be enabled or disabled on a single access. If Priority Queueing
is disabled, then these bits have no effect. These bits read back the
enabled status for the TX Priority Queues.
Set to 1 to force the DP83820 to a soft reset state which disables the
transmitter and receiver, reinitializes the FIFOs, and resets all affected
registers to their soft reset state. This operation implies both a TXR and a
RXR. This bit will read back a 1 during the reset operation, and be cleared
to 0 by the hardware when the reset operation is complete.
Setting this bit to a 1 forces the DP83820 to generate a hardware interrupt.
This interrupt is mask-able via the IMR.
unused
When set to a 1, this bit causes the current packet reception to be aborted,
the receive data and status FIFOs to be flushed, and the receive state
machine to enter the idle state (RXE goes to 0). This is a write-only bit and
is always read back as 0.
40
www.national.com
Direct download click here
 

General Description
DP83820 is a single-chip 10/100/1000 Mb/s Ethernet Controller for the PCI bus. It is targeted at high
performance adapter cards and mother boards. The DP83820 fully implements the V2.2 66 MHz, 64-bit PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83820 can support full duplex 10/100/1000 Mb/s transmission and reception.

Features
— IEEE 802.3 Compliant, 66/33 Mhz, 64/32-bit PCI V2.2 MAC/BIU supports data rates from 1 Mb/s to 1000 Mb/s. This allows support for traditional 10 Mb/s Ethernet, 100 Mb/s Fast Ethernet, as well as 1000 Mb/s Gigabit Ethernet.
— Flexible, programmable Bus master - burst sizes of up to 256 dwords (1024 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98, PC99, and OnNow, including directed packets, Magic Packet with SecureOn, ARP packets, pattern match packets, and Phy status change
— GMII/MII provides IEEE 802.3 standard interface to support 10/100/1000 Mb/s physical layer devices
— Ten-Bit Interface (TBI) for support of 1000BASE-X
— Virtual LAN (VLAN) and long frame support. VLAN tag insertion support for transmit packets. VLAN tag detection and removal for receive packets
— 802.3x Full duplex flow control, including automatic transmission of Pause frames based on Rx FIFO thresholds
— IPv.4 checksum task off-loading. Supports checksum generation and verification of IP, TCP, and UDP headers
— 802.1D and 802.1Q priority queueing support. Supports multiple priority queues in both transmit and receive directions.
— Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 2,048 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns.
— Statistics gathered for support of RFC 1213 (MIB II), RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing CPU overhead for management.
— Internal 8 KB Transmit and 32 KB Receive data FIFOs
— Supports Jumbo packets
— Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Full Duplex support for 10/100/1000 Mb/s data rates
— 208-pin PQFP package
— Low power CMOS design
— 3.3V powered I/Os with 5V tolerant inputs
— JTAG Boundary Scan supported

Share Link : National-Semiconductor
All Rights Reserved © datasheetbank.com 2014 - 2018 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]