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DP83820BVUW-AB View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
DP83820BVUW-AB 10/100/1000 Mb/s PCI Ethernet Network Interface Controller National-Semiconductor
National ->Texas Instruments National-Semiconductor
DP83820BVUW-AB Datasheet PDF : 87 Pages
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4.0 Register Set (Continued)
CCh
CCSR Clockrun Control/Status Register
R/W
D0-DCh
Reserved
E0h
TBICR TBI Control Register
R/W
E4h
TBISR TBI Status Register
R/W
E8h
TANAR TBI Auto-Negotiation Advertisement Register
R/W
ECh
TANLPAR TBI Auto-Negotiation Link Partner Ability Register
R/W
F0h
TANER TBI Auto-Negotiation Expansion Register
R/W
F4h
TESR TBI Extended Status Register
R/W
F8-FCh
Reserved
100-1FCh
Alias of 00-FCh (memory mapped only)
R/W
200-2FC Config. 32-bit Read access of PCI Configuration Registers (memory mapped only)
RO
Registers
300-3FC
Alias of 200-2FC. 32-bit Read access of PCI Configuration Registers (memory
RO
mapped only)
4.2.1 Command Register
This register is used for issuing commands to the DP83820. These commands are issued by setting the corresponding
bits for the function. A global software reset along with individual reset and enable/disable for transmitter and receiver are
provided here. Setting control bits to 0 has no effect, therefore there is no need for Read/modify/writes to this register.
Tag: CR
Size: 32 bits
Hard Reset: 00000000h
Offset: 0000h
Access: Read Write
Soft Reset: 00000000h
bit
31-17
16-13
12-9
8
7
6
5
tag
description
RXPRI RX Priority Queue Select
TXPRI TX Priority Queue Select
RST
Reset
SWI
Software Interrupt
RXR
Receiver Reset
usage
unused
If Receive Priority Queueing is enabled, these bits indicate which queues
should be enabled or disabled if the RXE or RXD bits are set during a write
to this register. Bit 16 corresponds to Priority Queue 3 (highest priority),
while bit 13 corresponds to Priority Queue 0 (lowest priority). Multiple
queues can be enabled or disabled on a single access. If Priority Queueing
is disabled, then these bits have no effect. These bits read back the
enabled status for the RX Priority Queues.
If Transmit Priority Queueing is enabled, these bits indicate which queues
should be enabled or disabled if the TXE or TXD bits are set during a write
to this register. Bit 12 corresponds to Priority Queue 3 (highest priority),
while bit 9 corresponds to Priority Queue 0 (lowest priority). Multiple
queues can be enabled or disabled on a single access. If Priority Queueing
is disabled, then these bits have no effect. These bits read back the
enabled status for the TX Priority Queues.
Set to 1 to force the DP83820 to a soft reset state which disables the
transmitter and receiver, reinitializes the FIFOs, and resets all affected
registers to their soft reset state. This operation implies both a TXR and a
RXR. This bit will read back a 1 during the reset operation, and be cleared
to 0 by the hardware when the reset operation is complete.
Setting this bit to a 1 forces the DP83820 to generate a hardware interrupt.
This interrupt is mask-able via the IMR.
unused
When set to a 1, this bit causes the current packet reception to be aborted,
the receive data and status FIFOs to be flushed, and the receive state
machine to enter the idle state (RXE goes to 0). This is a write-only bit and
is always read back as 0.
40
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