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DP83820BVUW-AB View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
DP83820BVUW-AB 10/100/1000 Mb/s PCI Ethernet Network Interface Controller National-Semiconductor
National ->Texas Instruments National-Semiconductor
DP83820BVUW-AB Datasheet PDF : 87 Pages
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4.0 Register Set (Continued)
4.1.11 Configuration Interrupt Select Register
This register stores the interrupt line number as identified by the POST software that is connected to the interrupt
controller as well as DP83820 desired settings for maximum latency and minimum grant. Max latency and Min. latency
can be loaded from the EEPROM
Tag: CFGINT
Size: 32 bits
Hard Reset: 340b0100h
Offset: 3Ch
Access: Read Write
Soft Reset: unchanged
bit
31-24
tag
MXLAT
description
Maximum Latency
23-16
MNGNT Minimum Grant
15-8
7-0
IPIN
ILINE
Interrupt Pin
Interrupt Line
usage
The DP83820 desired setting for Max Latency. The DP83820 will initialize
this field to 52d (13 usec). The value in this register can be loaded from the
EEPROM.
The DP83820 desired setting for Minimum Grant. The DP83820 will
initialize this field to 11d (2.75 usec). The value in this register can be
loaded from the EEPROM.
Read Only, always return 0000 0001 (INTA)
Set to which line on the interrupt controller that the DP83820's interrupt pin
is connected to.
4.1.12 Power Management Capabilities Register
This register provides information on the capabilities of the functions related to power management. This register also
contains a pointer to the next item in the capabilities list and the capability ID for Power Management. This register is only
visible if CFGCS[4] is set.
Tag: PMCAP
Size: 32 bits
Hard Reset: FF820001
Offset: 40h
Access: Read Only
Soft Reset: unchanged
bit
31-27
26
25
24-22
21
tag
description
usage
PMES
PME Support
This 5 bit field indicates the power states in which DP83820 may assert
PMEN. A 1 indicates PMEN is enabled for that state, a 0 indicates PMEN is
inhibited in that state.
XXXX1 - PMEN can be asserted from state D0
XXX1X - PMEN can be asserted from state D1
XX1XX - PMEN can be asserted from state D2
X1XXX - PMEN can be asserted from state D3hot
1XXXX - PMEN can be asserted from state D3cold
The DP83820 will only report PME support for D3cold if auxiliary power is
detected on the 3VAUX pin, in addition this value can be loaded from the
EEPROM when in the D3cold state.
D2S
D2 Support
This bit is set to a 1 when the DP83820 supports the D2 state.
D1S
D1 Support
This bit is set to a 1 when the DP83820 supports the D1 state.
AUX_CURRENT 3 bit field for aux current
requirement.
Aux_Current - This 3 bit field reports the 3.3Vaux auxiliary current
requirements for the PCI function.
If PMEN generation from D3cold is not supported by the
function(PMCAP[31]), this field returns a value of 000bwhen read.
Bit
3.3Vaux
8 7 6 Max. Current Required
110
320 mA
000
0 (self powered)
DSI
Device Specific Initialization This bit is set to 1 to indicate to the system that initialization of the DP83820
device is required (beyond the standard PCI configuration header) before
the generic class device driver is able to use it. A 1 indicates that DP83820
requires a DSI sequence following transition to the D0 uninitialized state.
This bit can be loaded from the EEPROM.
37
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