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DP83820BVUW-AB View Datasheet(PDF) - National ->Texas Instruments

Part NameDP83820BVUW-AB National-Semiconductor
National ->Texas Instruments National-Semiconductor
Description10/100/1000 Mb/s PCI Ethernet Network Interface Controller
DP83820BVUW-AB Datasheet PDF : 87 Pages
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4.0 Register Set (Continued)
4.1.11 Configuration Interrupt Select Register
This register stores the interrupt line number as identified by the POST software that is connected to the interrupt
controller as well as DP83820 desired settings for maximum latency and minimum grant. Max latency and Min. latency
can be loaded from the EEPROM
Size: 32 bits
Hard Reset: 340b0100h
Offset: 3Ch
Access: Read Write
Soft Reset: unchanged
Maximum Latency
MNGNT Minimum Grant
Interrupt Pin
Interrupt Line
The DP83820 desired setting for Max Latency. The DP83820 will initialize
this field to 52d (13 usec). The value in this register can be loaded from the
The DP83820 desired setting for Minimum Grant. The DP83820 will
initialize this field to 11d (2.75 usec). The value in this register can be
loaded from the EEPROM.
Read Only, always return 0000 0001 (INTA)
Set to which line on the interrupt controller that the DP83820's interrupt pin
is connected to.
4.1.12 Power Management Capabilities Register
This register provides information on the capabilities of the functions related to power management. This register also
contains a pointer to the next item in the capabilities list and the capability ID for Power Management. This register is only
visible if CFGCS[4] is set.
Size: 32 bits
Hard Reset: FF820001
Offset: 40h
Access: Read Only
Soft Reset: unchanged
PME Support
This 5 bit field indicates the power states in which DP83820 may assert
PMEN. A 1 indicates PMEN is enabled for that state, a 0 indicates PMEN is
inhibited in that state.
XXXX1 - PMEN can be asserted from state D0
XXX1X - PMEN can be asserted from state D1
XX1XX - PMEN can be asserted from state D2
X1XXX - PMEN can be asserted from state D3hot
1XXXX - PMEN can be asserted from state D3cold
The DP83820 will only report PME support for D3cold if auxiliary power is
detected on the 3VAUX pin, in addition this value can be loaded from the
EEPROM when in the D3cold state.
D2 Support
This bit is set to a 1 when the DP83820 supports the D2 state.
D1 Support
This bit is set to a 1 when the DP83820 supports the D1 state.
AUX_CURRENT 3 bit field for aux current
Aux_Current - This 3 bit field reports the 3.3Vaux auxiliary current
requirements for the PCI function.
If PMEN generation from D3cold is not supported by the
function(PMCAP[31]), this field returns a value of 000bwhen read.
8 7 6 Max. Current Required
320 mA
0 (self powered)
Device Specific Initialization This bit is set to 1 to indicate to the system that initialization of the DP83820
device is required (beyond the standard PCI configuration header) before
the generic class device driver is able to use it. A 1 indicates that DP83820
requires a DSI sequence following transition to the D0 uninitialized state.
This bit can be loaded from the EEPROM.
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General Description
DP83820 is a single-chip 10/100/1000 Mb/s Ethernet Controller for the PCI bus. It is targeted at high
performance adapter cards and mother boards. The DP83820 fully implements the V2.2 66 MHz, 64-bit PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83820 can support full duplex 10/100/1000 Mb/s transmission and reception.

— IEEE 802.3 Compliant, 66/33 Mhz, 64/32-bit PCI V2.2 MAC/BIU supports data rates from 1 Mb/s to 1000 Mb/s. This allows support for traditional 10 Mb/s Ethernet, 100 Mb/s Fast Ethernet, as well as 1000 Mb/s Gigabit Ethernet.
— Flexible, programmable Bus master - burst sizes of up to 256 dwords (1024 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98, PC99, and OnNow, including directed packets, Magic Packet with SecureOn, ARP packets, pattern match packets, and Phy status change
— GMII/MII provides IEEE 802.3 standard interface to support 10/100/1000 Mb/s physical layer devices
— Ten-Bit Interface (TBI) for support of 1000BASE-X
— Virtual LAN (VLAN) and long frame support. VLAN tag insertion support for transmit packets. VLAN tag detection and removal for receive packets
— 802.3x Full duplex flow control, including automatic transmission of Pause frames based on Rx FIFO thresholds
— IPv.4 checksum task off-loading. Supports checksum generation and verification of IP, TCP, and UDP headers
— 802.1D and 802.1Q priority queueing support. Supports multiple priority queues in both transmit and receive directions.
— Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 2,048 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns.
— Statistics gathered for support of RFC 1213 (MIB II), RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing CPU overhead for management.
— Internal 8 KB Transmit and 32 KB Receive data FIFOs
— Supports Jumbo packets
— Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Full Duplex support for 10/100/1000 Mb/s data rates
— 208-pin PQFP package
— Low power CMOS design
— 3.3V powered I/Os with 5V tolerant inputs
— JTAG Boundary Scan supported

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