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DP83820BVUW-AB View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
DP83820BVUW-AB 10/100/1000 Mb/s PCI Ethernet Network Interface Controller National-Semiconductor
National ->Texas Instruments National-Semiconductor
DP83820BVUW-AB Datasheet PDF : 87 Pages
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4.0 Register Set (Continued)
4.1.3 Configuration Revision ID Register
This register stores the silicon revision number, revision number of software interface specification and lets the
configuration software know that it is an Ethernet controller in the class of network controllers.
Tag: CFGRID
Size: 32 bits
Hard Reset: 02000000h
Offset: 08h
Access: Read Only
Soft Reset: Unchanged
bit
31-24
23-16
15-8
7-0
tag
BASECL
SUBCL
PROGIF
REVID
description
Base Class
Sub Class
Programming IF
Silicon Revision
usage
Returns 02h which specifies a network controller.
Returns 00h which specifies an Ethernet controller.
Returns 00h which specifies the first release of the DP83820.
Returns 00h which specifies the silicon revision.
4.1.4 Configuration Latency Timer Register
This register gives status and controls such miscellaneous functions as BIST, Latency timer and Cache line size.
Tag: CFGLAT
Size: 32 bits
Hard Reset: 00000000h
Offset: 0Ch
Access: Read Write
Soft Reset: Unchanged
bit
31
30
29-16
15-8
7-0
tag
BISTCAP
BISTEN
LAT
description
BIST Capable
BIST Enable
Reserved
Latency Timer
CLS
Cache Line Size
usage
Reads will always return 0.
Reads will return a 0, writes are ignored.
Reads will return a 0, writes are ignored.
Set by software to the number of PCI clocks that DP83820 may hold the
PCI bus.
Set to the value of the system cache line size in dwords. Acceptable values
are powers of 2 less than or equal to 128. All other values will be
recognized as 0.
DP83820 Bus Master Operations:
Based on cache line size, the DP83820 will use the following PCI commands for bus mastered transfers:
0110 - Mem Read
Single dword read transfers
1110 - Mem Read Line
Read More than 1 dword but not across a cacheline boundary
1100 - Mem Read Multiple Read transfers that cross a cacheline boundary
0111 - Mem Write
Writes that do not exactly overwrite 1 or more cachelines
1111 - Mem Write Invalidate Writes that exactly overwrite 1 or more cachelines
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