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DP83820BVUW-AB View Datasheet(PDF) - National ->Texas Instruments

Part NameDP83820BVUW-AB National-Semiconductor
National ->Texas Instruments National-Semiconductor
Description10/100/1000 Mb/s PCI Ethernet Network Interface Controller
DP83820BVUW-AB Datasheet PDF : 87 Pages
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4.0 Register Set (Continued)
4.1.3 Configuration Revision ID Register
This register stores the silicon revision number, revision number of software interface specification and lets the
configuration software know that it is an Ethernet controller in the class of network controllers.
Tag: CFGRID
Size: 32 bits
Hard Reset: 02000000h
Offset: 08h
Access: Read Only
Soft Reset: Unchanged
bit
31-24
23-16
15-8
7-0
tag
BASECL
SUBCL
PROGIF
REVID
description
Base Class
Sub Class
Programming IF
Silicon Revision
usage
Returns 02h which specifies a network controller.
Returns 00h which specifies an Ethernet controller.
Returns 00h which specifies the first release of the DP83820.
Returns 00h which specifies the silicon revision.
4.1.4 Configuration Latency Timer Register
This register gives status and controls such miscellaneous functions as BIST, Latency timer and Cache line size.
Tag: CFGLAT
Size: 32 bits
Hard Reset: 00000000h
Offset: 0Ch
Access: Read Write
Soft Reset: Unchanged
bit
31
30
29-16
15-8
7-0
tag
BISTCAP
BISTEN
LAT
description
BIST Capable
BIST Enable
Reserved
Latency Timer
CLS
Cache Line Size
usage
Reads will always return 0.
Reads will return a 0, writes are ignored.
Reads will return a 0, writes are ignored.
Set by software to the number of PCI clocks that DP83820 may hold the
PCI bus.
Set to the value of the system cache line size in dwords. Acceptable values
are powers of 2 less than or equal to 128. All other values will be
recognized as 0.
DP83820 Bus Master Operations:
Based on cache line size, the DP83820 will use the following PCI commands for bus mastered transfers:
0110 - Mem Read
Single dword read transfers
1110 - Mem Read Line
Read More than 1 dword but not across a cacheline boundary
1100 - Mem Read Multiple Read transfers that cross a cacheline boundary
0111 - Mem Write
Writes that do not exactly overwrite 1 or more cachelines
1111 - Mem Write Invalidate Writes that exactly overwrite 1 or more cachelines
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General Description
DP83820 is a single-chip 10/100/1000 Mb/s Ethernet Controller for the PCI bus. It is targeted at high
performance adapter cards and mother boards. The DP83820 fully implements the V2.2 66 MHz, 64-bit PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83820 can support full duplex 10/100/1000 Mb/s transmission and reception.

Features
— IEEE 802.3 Compliant, 66/33 Mhz, 64/32-bit PCI V2.2 MAC/BIU supports data rates from 1 Mb/s to 1000 Mb/s. This allows support for traditional 10 Mb/s Ethernet, 100 Mb/s Fast Ethernet, as well as 1000 Mb/s Gigabit Ethernet.
— Flexible, programmable Bus master - burst sizes of up to 256 dwords (1024 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98, PC99, and OnNow, including directed packets, Magic Packet with SecureOn, ARP packets, pattern match packets, and Phy status change
— GMII/MII provides IEEE 802.3 standard interface to support 10/100/1000 Mb/s physical layer devices
— Ten-Bit Interface (TBI) for support of 1000BASE-X
— Virtual LAN (VLAN) and long frame support. VLAN tag insertion support for transmit packets. VLAN tag detection and removal for receive packets
— 802.3x Full duplex flow control, including automatic transmission of Pause frames based on Rx FIFO thresholds
— IPv.4 checksum task off-loading. Supports checksum generation and verification of IP, TCP, and UDP headers
— 802.1D and 802.1Q priority queueing support. Supports multiple priority queues in both transmit and receive directions.
— Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 2,048 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns.
— Statistics gathered for support of RFC 1213 (MIB II), RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing CPU overhead for management.
— Internal 8 KB Transmit and 32 KB Receive data FIFOs
— Supports Jumbo packets
— Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Full Duplex support for 10/100/1000 Mb/s data rates
— 208-pin PQFP package
— Low power CMOS design
— 3.3V powered I/Os with 5V tolerant inputs
— JTAG Boundary Scan supported

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