datasheetbank_Logo    Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :

DP83820BVUW-AB View Datasheet(PDF) - National ->Texas Instruments

Part NameDP83820BVUW-AB National-Semiconductor
National ->Texas Instruments National-Semiconductor
Description10/100/1000 Mb/s PCI Ethernet Network Interface Controller
DP83820BVUW-AB Datasheet PDF : 87 Pages
First Prev 31 32 33 34 35 36 37 38 39 40 Next Last
4.0 Register Set
4.1 Configuration Registers
The DP83820 implements a PCI version 2.2 configuration register space. This allows a PCI BIOS to "soft" configure the
DP83820. Software Reset has no effect on configuration registers. Hardware Reset returns all configuration registers to
their hardware reset state. For all unused registers, writes are ignored, and reads return 0.
Table 4-1 Configuration Register Map
offset
00h
04h
08h
0Ch
10h
14h
18
1Ch-28h
2Ch
30h
34h
38h
3Ch
40h
44h
48-FFh
tag
description
CFGID Configuration Identification Register
CFGCS Configuration Command and Status Register
CFGRID Configuration Revision ID Register
CFGLAT Configuration Latency Timer Register
CFGIOA Configuration IO Base Address Register
CFGMA Configuration Memory Address Register
CFGMA1 Configuration Memory Address High Dword Register
Reserved (reads return zero)
CFGSID Configuration Subsystem Identification Register
CFGROM Boot ROM configuration register
CAPPTR Capabilities Pointer Register
Reserved (reads return zero)
CFGINT Configuration Interrupt Select Register
PMCAP Power Management Capabilities Register
PMCS Power Management Control and Status Register
Reserved (reads return zero)
access
RO
R/W
RO
RO
R/W
R/W
R/W
RO
R/W
RO
R/W
RO
R/W
4.1.1 Configuration Identification Register
This register identifies the DP83820 Controller to PCI system software.
Tag: CFGID
Size: 32 bits
Offset: 00h
Access: Read Only
Hard Reset: 0022100B
Soft Reset: Unchanged
bit
31-16
15-0
tag
DEVID
description
Device ID
VENID Vendor ID
usage
This field is read-only and is set to the device ID assigned by NSC to the
DP83820, which is 0022h.
This field is read-only and is set to a value of 100Bh which is National
Semiconductor's PCI Vendor ID.
32
www.national.com
Direct download click here
 

General Description
DP83820 is a single-chip 10/100/1000 Mb/s Ethernet Controller for the PCI bus. It is targeted at high
performance adapter cards and mother boards. The DP83820 fully implements the V2.2 66 MHz, 64-bit PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83820 can support full duplex 10/100/1000 Mb/s transmission and reception.

Features
— IEEE 802.3 Compliant, 66/33 Mhz, 64/32-bit PCI V2.2 MAC/BIU supports data rates from 1 Mb/s to 1000 Mb/s. This allows support for traditional 10 Mb/s Ethernet, 100 Mb/s Fast Ethernet, as well as 1000 Mb/s Gigabit Ethernet.
— Flexible, programmable Bus master - burst sizes of up to 256 dwords (1024 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98, PC99, and OnNow, including directed packets, Magic Packet with SecureOn, ARP packets, pattern match packets, and Phy status change
— GMII/MII provides IEEE 802.3 standard interface to support 10/100/1000 Mb/s physical layer devices
— Ten-Bit Interface (TBI) for support of 1000BASE-X
— Virtual LAN (VLAN) and long frame support. VLAN tag insertion support for transmit packets. VLAN tag detection and removal for receive packets
— 802.3x Full duplex flow control, including automatic transmission of Pause frames based on Rx FIFO thresholds
— IPv.4 checksum task off-loading. Supports checksum generation and verification of IP, TCP, and UDP headers
— 802.1D and 802.1Q priority queueing support. Supports multiple priority queues in both transmit and receive directions.
— Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 2,048 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns.
— Statistics gathered for support of RFC 1213 (MIB II), RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing CPU overhead for management.
— Internal 8 KB Transmit and 32 KB Receive data FIFOs
— Supports Jumbo packets
— Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Full Duplex support for 10/100/1000 Mb/s data rates
— 208-pin PQFP package
— Low power CMOS design
— 3.3V powered I/Os with 5V tolerant inputs
— JTAG Boundary Scan supported

Share Link : National-Semiconductor
@ 2014 - 2018  [ Home ] [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]