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DP83820BVUW-AB View Datasheet(PDF) - National ->Texas Instruments

Part NameDP83820BVUW-AB National-Semiconductor
National ->Texas Instruments National-Semiconductor
Description10/100/1000 Mb/s PCI Ethernet Network Interface Controller
DP83820BVUW-AB Datasheet PDF : 87 Pages
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3.0 Functional Description (Continued)
was used to describe the packet, then completion
status is updated only in the last descriptor.
Intermediate descriptors only have the OWN bits
9. If the link field of the descriptor is non-zero, the state
machine advances to the next descriptor and
continues. When reading the next descriptor, if the
OWN bit is not set, the state machine will halt and
wait for TXEN to be set again.
10. If the link field is NULL, the transmit state machine
suspends, waiting for the TXEN bit in the CR register
to be set. If the TXDP register is written to, the CTDD
flag will be cleared. When the TXEN bit is set, the
state machine will examine CTDD. If CTDD is set,
the state machine will "refresh" the link field of the
current descriptor. It will then follow the link field to
any new descriptors that have been added to the end
of the list. If CTDD is clear (implying that TXDP has
been written to), the state machine will start by
reading in the descriptor pointed to by TXDP. Transmit Data Flow with Priority Queueing
The transmit architecture with Priority Queueing is the
same with a few minor differences:
Driver keeps a separate list for each descriptor queue.
When setting the TXEN bit, the driver must also set the
appropriate TXPRI bit for the priority queue or queues to
which descriptors are being appended.
Upon completion of a packet, the transmit state machine
first determines what the highest priority descriptor is
available based on non-zero link fields and TXEN bits. It
then follows the appropriate link or reads a new
descriptor for the next packet to be transmitted.
3.13.4 Receive Architecture
The receive architecture is as "symmetrical" to the transmit
architecture as possible. As is done in the transmitter, the
receive architecture can support a single descriptor queue
or multiple descriptor queues for handling priority traffic.
When the amount of receive data in the RxDataFIFO is
more than the RxDrainThreshold, or the RxDataFIFO
contains a complete packet, then the state machine begins
filling received buffers in host memory.
Figure 3-17 Receive Architecture without Priority Queueing
Recieve Descriptor List
Current Rx Desc Ptr
Rx Desc Cache
Rx Data FIFO
Without Priority Queueing, the device will transfer packets
to a single Descriptor list. Only one descriptor pointer is
required. The receive buffer manager prefetches receive
descriptors to prepare for incoming packets. When the
RXEN bit is set to 1 in the CR register (regardless of the
current state), and the DP83820 receive state machine is
idle, then DP83820 will read the contents of the descriptor
referenced by RXDP into the Rx Descriptor Cache. The Rx
Descriptor Cache allows the DP83820 to read an entire
descriptor in a single burst, and reduces the number of bus
accesses required for fragment information to 1. The
DP83820 Rx Descriptor Cache holds a single buffer
pointer/count combination.
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General Description
DP83820 is a single-chip 10/100/1000 Mb/s Ethernet Controller for the PCI bus. It is targeted at high
performance adapter cards and mother boards. The DP83820 fully implements the V2.2 66 MHz, 64-bit PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83820 can support full duplex 10/100/1000 Mb/s transmission and reception.

— IEEE 802.3 Compliant, 66/33 Mhz, 64/32-bit PCI V2.2 MAC/BIU supports data rates from 1 Mb/s to 1000 Mb/s. This allows support for traditional 10 Mb/s Ethernet, 100 Mb/s Fast Ethernet, as well as 1000 Mb/s Gigabit Ethernet.
— Flexible, programmable Bus master - burst sizes of up to 256 dwords (1024 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98, PC99, and OnNow, including directed packets, Magic Packet with SecureOn, ARP packets, pattern match packets, and Phy status change
— GMII/MII provides IEEE 802.3 standard interface to support 10/100/1000 Mb/s physical layer devices
— Ten-Bit Interface (TBI) for support of 1000BASE-X
— Virtual LAN (VLAN) and long frame support. VLAN tag insertion support for transmit packets. VLAN tag detection and removal for receive packets
— 802.3x Full duplex flow control, including automatic transmission of Pause frames based on Rx FIFO thresholds
— IPv.4 checksum task off-loading. Supports checksum generation and verification of IP, TCP, and UDP headers
— 802.1D and 802.1Q priority queueing support. Supports multiple priority queues in both transmit and receive directions.
— Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 2,048 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns.
— Statistics gathered for support of RFC 1213 (MIB II), RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing CPU overhead for management.
— Internal 8 KB Transmit and 32 KB Receive data FIFOs
— Supports Jumbo packets
— Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Full Duplex support for 10/100/1000 Mb/s data rates
— 208-pin PQFP package
— Low power CMOS design
— 3.3V powered I/Os with 5V tolerant inputs
— JTAG Boundary Scan supported

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