|DP83820BVUW-AB||10/100/1000 Mb/s PCI Ethernet Network Interface Controller|
National ->Texas Instruments
|DP83820BVUW-AB Datasheet PDF : 87 Pages |
3.0 Functional Description (Continued)
was used to describe the packet, then completion
status is updated only in the last descriptor.
Intermediate descriptors only have the OWN bits
9. If the link field of the descriptor is non-zero, the state
machine advances to the next descriptor and
continues. When reading the next descriptor, if the
OWN bit is not set, the state machine will halt and
wait for TXEN to be set again.
10. If the link field is NULL, the transmit state machine
suspends, waiting for the TXEN bit in the CR register
to be set. If the TXDP register is written to, the CTDD
flag will be cleared. When the TXEN bit is set, the
state machine will examine CTDD. If CTDD is set,
the state machine will "refresh" the link field of the
current descriptor. It will then follow the link field to
any new descriptors that have been added to the end
of the list. If CTDD is clear (implying that TXDP has
been written to), the state machine will start by
reading in the descriptor pointed to by TXDP.
188.8.131.52 Transmit Data Flow with Priority Queueing
The transmit architecture with Priority Queueing is the
same with a few minor differences:
— Driver keeps a separate list for each descriptor queue.
— When setting the TXEN bit, the driver must also set the
appropriate TXPRI bit for the priority queue or queues to
which descriptors are being appended.
— Upon completion of a packet, the transmit state machine
first determines what the highest priority descriptor is
available based on non-zero link fields and TXEN bits. It
then follows the appropriate link or reads a new
descriptor for the next packet to be transmitted.
3.13.4 Receive Architecture
The receive architecture is as "symmetrical" to the transmit
architecture as possible. As is done in the transmitter, the
receive architecture can support a single descriptor queue
or multiple descriptor queues for handling priority traffic.
When the amount of receive data in the RxDataFIFO is
more than the RxDrainThreshold, or the RxDataFIFO
contains a complete packet, then the state machine begins
filling received buffers in host memory.
Figure 3-17 Receive Architecture without Priority Queueing
Recieve Descriptor List
Current Rx Desc Ptr
Rx Desc Cache
Rx Data FIFO
Without Priority Queueing, the device will transfer packets
to a single Descriptor list. Only one descriptor pointer is
required. The receive buffer manager prefetches receive
descriptors to prepare for incoming packets. When the
RXEN bit is set to 1 in the CR register (regardless of the
current state), and the DP83820 receive state machine is
idle, then DP83820 will read the contents of the descriptor
referenced by RXDP into the Rx Descriptor Cache. The Rx
Descriptor Cache allows the DP83820 to read an entire
descriptor in a single burst, and reduces the number of bus
accesses required for fragment information to 1. The
DP83820 Rx Descriptor Cache holds a single buffer
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