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DP83820BVUW-AB View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
DP83820BVUW-AB 10/100/1000 Mb/s PCI Ethernet Network Interface Controller National-Semiconductor
National ->Texas Instruments National-Semiconductor
DP83820BVUW-AB Datasheet PDF : 87 Pages
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3.0 Functional Description (Continued)
RFC 1213
software, increment on
receive packets with
cmdsts.TXA set
TXExcessiveCollisions RFC 1643,
802.3 LM
802.3 LM
RFC 1643,
802.3 LM
RFC 1643,
802.3 LM
RFC 1643
software, increment on
transmit packets with
cmdsts.EC set.
software, increment on
transmit packets with
cmdsts.ED set.
software, increment on
transmit packets with
cmdsts.OWC set.
software, increment on
transmit packets with
cmdsts.CRS set.
hardware, see
This counter is incremented for each packet
encountering errors during transmission.
This count does include transmissions
aborted manually and due to FIFO
underruns, but does not include packets
which experience less than 16 in-window
This counter is incremented for each
transmission aborted after experiencing 16
in-window collisions.
This counter is incremented for each
transmission aborted due to a time-out of
the excessive deferral timer (3.2ms).
This counter is incremented for each
transmission which is aborted due to an
out-of-window collision.
This counter is incremented for each
transmission on which carrier is not
detected after the start of transmission, or
carrier sense is lost during transmission.
This counter is incremented when the
collision heartbeat pulse is not detected
from by the PMD after a transmission.
3.13 Buffer Management
The buffer management scheme used on the DP83820
allows quick, simple and efficient use of the frame buffer
memory. Frames are saved in similar formats for both
transmit and receive. The buffer management scheme also
uses separate buffers and descriptors for packet
information. This allows effective transfers of data from the
receive buffer to the transmit buffer by simply transferring
the descriptor from the receive queue to the transmit
The format of the descriptors allows the packets to be
saved in a number of configurations. A packet can be
stored in memory with a single descriptor and a single
packet fragment, or multiple descriptors with single
fragments. This flexibility allows the user to configure the
DP83820 to maximize efficiency. Architecture of the
specific systems buffer memory, as well as the nature of
network traffic, will determine the most suitable
configuration of packet descriptors and fragments.
3.13.1 Overview
The buffer management design has the following goals:
efficient use of the PCI bus (the overhead of the buffer
management technique is minimal),
low CPU utilization,
Descriptors may be either per-packet or per-packet-
fragment. Each descriptor may describe one packet
fragment. Receive and transmit descriptors are
3.13.2 Descriptor Format
DP83820 uses a symmetrical format for transmit and
receive descriptors. In bridging and switching applications
this symmetry allows software to forward packets by simply
moving the list of descriptors that describe a single
received packet from the receive list of one MAC to the
transmit list of another. Descriptors must be aligned on a
64-bit boundary.
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