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DP83820BVUW-AB View Datasheet(PDF) - National ->Texas Instruments

Part NameDP83820BVUW-AB National-Semiconductor
National ->Texas Instruments National-Semiconductor
Description10/100/1000 Mb/s PCI Ethernet Network Interface Controller
DP83820BVUW-AB Datasheet PDF : 87 Pages
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3.0 Functional Description (Continued)
TXPktsErrored
RFC 1213
software, increment on
receive packets with
cmdsts.TXA set
TXExcessiveCollisions RFC 1643,
802.3 LM
TXExcessiveDeferral
802.3 LM
TXOWC
TXCSErrors
RFC 1643,
802.3 LM
RFC 1643,
802.3 LM
TXSQEErrors
RFC 1643
software, increment on
transmit packets with
cmdsts.EC set.
software, increment on
transmit packets with
cmdsts.ED set.
software, increment on
transmit packets with
cmdsts.OWC set.
software, increment on
transmit packets with
cmdsts.CRS set.
hardware, see
MIB:TxSQEErrors
This counter is incremented for each packet
encountering errors during transmission.
This count does include transmissions
aborted manually and due to FIFO
underruns, but does not include packets
which experience less than 16 in-window
collisions.
This counter is incremented for each
transmission aborted after experiencing 16
in-window collisions.
This counter is incremented for each
transmission aborted due to a time-out of
the excessive deferral timer (3.2ms).
This counter is incremented for each
transmission which is aborted due to an
out-of-window collision.
This counter is incremented for each
transmission on which carrier is not
detected after the start of transmission, or
carrier sense is lost during transmission.
This counter is incremented when the
collision heartbeat pulse is not detected
from by the PMD after a transmission.
3.13 Buffer Management
The buffer management scheme used on the DP83820
allows quick, simple and efficient use of the frame buffer
memory. Frames are saved in similar formats for both
transmit and receive. The buffer management scheme also
uses separate buffers and descriptors for packet
information. This allows effective transfers of data from the
receive buffer to the transmit buffer by simply transferring
the descriptor from the receive queue to the transmit
queue.
The format of the descriptors allows the packets to be
saved in a number of configurations. A packet can be
stored in memory with a single descriptor and a single
packet fragment, or multiple descriptors with single
fragments. This flexibility allows the user to configure the
DP83820 to maximize efficiency. Architecture of the
specific systems buffer memory, as well as the nature of
network traffic, will determine the most suitable
configuration of packet descriptors and fragments.
3.13.1 Overview
The buffer management design has the following goals:
simplicity
efficient use of the PCI bus (the overhead of the buffer
management technique is minimal),
low CPU utilization,
flexibility.
Descriptors may be either per-packet or per-packet-
fragment. Each descriptor may describe one packet
fragment. Receive and transmit descriptors are
symmetrical.
3.13.2 Descriptor Format
DP83820 uses a symmetrical format for transmit and
receive descriptors. In bridging and switching applications
this symmetry allows software to forward packets by simply
moving the list of descriptors that describe a single
received packet from the receive list of one MAC to the
transmit list of another. Descriptors must be aligned on a
64-bit boundary.
18
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General Description
DP83820 is a single-chip 10/100/1000 Mb/s Ethernet Controller for the PCI bus. It is targeted at high
performance adapter cards and mother boards. The DP83820 fully implements the V2.2 66 MHz, 64-bit PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83820 can support full duplex 10/100/1000 Mb/s transmission and reception.

Features
— IEEE 802.3 Compliant, 66/33 Mhz, 64/32-bit PCI V2.2 MAC/BIU supports data rates from 1 Mb/s to 1000 Mb/s. This allows support for traditional 10 Mb/s Ethernet, 100 Mb/s Fast Ethernet, as well as 1000 Mb/s Gigabit Ethernet.
— Flexible, programmable Bus master - burst sizes of up to 256 dwords (1024 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98, PC99, and OnNow, including directed packets, Magic Packet with SecureOn, ARP packets, pattern match packets, and Phy status change
— GMII/MII provides IEEE 802.3 standard interface to support 10/100/1000 Mb/s physical layer devices
— Ten-Bit Interface (TBI) for support of 1000BASE-X
— Virtual LAN (VLAN) and long frame support. VLAN tag insertion support for transmit packets. VLAN tag detection and removal for receive packets
— 802.3x Full duplex flow control, including automatic transmission of Pause frames based on Rx FIFO thresholds
— IPv.4 checksum task off-loading. Supports checksum generation and verification of IP, TCP, and UDP headers
— 802.1D and 802.1Q priority queueing support. Supports multiple priority queues in both transmit and receive directions.
— Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 2,048 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns.
— Statistics gathered for support of RFC 1213 (MIB II), RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing CPU overhead for management.
— Internal 8 KB Transmit and 32 KB Receive data FIFOs
— Supports Jumbo packets
— Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Full Duplex support for 10/100/1000 Mb/s data rates
— 208-pin PQFP package
— Low power CMOS design
— 3.3V powered I/Os with 5V tolerant inputs
— JTAG Boundary Scan supported

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