HYS64V16220GU View Datasheet(PDF) - Siemens AG

Part Name

Description

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HYS64V16220GU

3.3 V 8M × 64/72-Bit 1 Bank SDRAM Module, 3.3 V 16M × 64/72-Bit 2 Bank SDRAM Module

Siemens AG 

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

Notes

1. The specified values are valid when addresses are changed no more than once during tCK(MIN.)

and when No Operation commands are registered on every rising clock edge during tRC(MIN.).

Values are shown per module bank.

2. The specified values are valid when data inputs (DQ’s) are stable during tRC(MIN.).

3. All AC characteristics are shown for device level.

An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must

be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can

begin.

4. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover

point. The transition time is measured between VIH and VIL. All AC measurements assume

tT = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are measured

with a 50 pF only, without any resistive termination and with a input signal of 1V/ns edge rate

between 0.8 V and 2.0 V.

.

t CH

CLOCK

2.4 V

0.4 V

t CL

tT

t SETUP

t HOLD

INPUT

1.4 V

OUTPUT

tAC

t LZ

tAC

t OH

1.4 V

t HZ

SPT03404

I/O

50 pF

Measurement conditions for

tAC and tOH

5. If clock rising time is longer than 1ns, a time (tT/2 – 0.5) ns has to be added to this parameter.

6. Rated at 1.5 V

7. If tT is longen than 1 ns, a time (tT – 1) ns has to be added to this parameter.

8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh

commands must be given to “wake-up“ the device.

9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after

CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied

once the Self Refresh Exit command is registered.

10.Referenced to the time which the output achieves the open circuit condition, not to output voltage

levels.

Semiconductor Group

11

1998-08-01

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