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DP83815 View Datasheet(PDF) - National ->Texas Instruments

Part NameDP83815 National-Semiconductor
National ->Texas Instruments National-Semiconductor
Description10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter™)
DP83815 Datasheet PDF : 108 Pages
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2.0 Pin Description (Continued)
PCI Bus Interface
I/O Parity Error: The DP83815 as a master or target will assert this
signal low to indicate a parity error on any incoming data (except for
special cycles). As a bus master, it will monitor this signal on all write
operations (except for special cycles).
O Request: The DP83815 will assert this signal low to request
ownership of the bus from the central arbiter.
I Reset: When this signal is asserted all outputs of DP83815 will be
tri-stated and the device will be put into a known state.
I/O System Error: This signal is asserted low by DP83815 during
address parity errors and system errors if enabled.
I/O Stop: This signal is asserted low by the target device to request the
master device to stop the current transaction.
I/O Target Ready: As a master, this signal indicates that the target is
ready for the data during write operation and with the data during
read operation. As a target, this signal will be asserted low when the
(target) device is ready to complete the current data phase
transaction. This signal is used in conjunction with the IRDYN signal.
Data transaction takes place at the rising edge of PCICLK when both
IRDYN and TRDYN are asserted low.
I/O Power Management Event/Clock Run Function: This pin is a dual
function pin. The function of this pin is determined by the
CLKRUN_EN bit 0 of the CLKRUN Control and Status register
(CCSR). Default operation of this pin is PMEN.
Power Management Event: This signal is asserted low by DP83815
to indicate that a power management event has occurred. For pin
connection please refer to Section 6.7.
Clock Run Function: In this mode, this pin is used to indicate when
the PCICLK will be stopped.
I PCI Auxiliary Voltage Sense: This pin is used to sense the
presence of a 3.3V auxiliary supply in order to define the PME
Support available. For pin connection please refer to Section 6.7.
This pin has an internal weak pull down.
I PCI bus power good: Connected to PCI bus 3.3V power (not
3.3Vaux), this pin is used to sense the presence of PCI bus power.
This pin has an internal weak pull down.
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General Description
DP83815 is a single-chip 10/100 Mb/s Ethernet Controller for the PCI bus. It is targeted at low-cost, high volume PC mother boards, adapter cards, and embedded systems. The DP83815 fully implements the V2.2 33 MHz PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83815 can support full duplex 10/100 Mb/s transmission and reception, with minimum interframe gap.
The DP83815 device is an integration of an enhanced version of the National Semiconductor PCI MAC/BIU (Media Access Controller/Bus Interface Unit) and a 3.3V CMOS physical layer interface.

— IEEE 802.3 Compliant, PCI V2.2 MAC/BIU supports traditional data rates of 10 Mb/s Ethernet and 100 Mb/s Fast Ethernet (via internal phy)
— Bus master - burst sizes of up to 128 dwords (512 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1.1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98,
PC99, SecureOn, and OnNow, including directed
packets, Magic Packet, VLAN packets, ARP packets,
pattern match packets, and Phy status change
— Clkrun function for PCI Mobile Design Guide
— Virtual LAN (VLAN) and long frame support
— Support for IEEE 802.3x Full duplex flow control
— Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 512 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns
— Statistics gathered for support of RFC 1213 (MIB II),
RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing
CPU overhead for management
— Internal 2 KB Transmit and 2 KB Receive data FIFOs
— Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Fully integrated IEEE 802.3/802.3u 3.3V CMOS physical layer
— IEEE 802.3 10BASE-T transceiver with integrated filters
— IEEE 802.3u 100BASE-TX transceiver
— Fully integrated ANSI X3.263 compliant TP-PMD physical sublayer with adaptive equalization and Baseline Wander compensation
— IEEE 802.3u Auto-Negotiation - advertised features configurable via EEPROM
— Full Duplex support for 10 and 100 Mb/s data rates
— Single 25 MHz reference clock
— 144-pin LQFP and 160-pin LBGA packages
— Low power 3.3V CMOS design with typical consumption of 561 mW operating, 380 mW during WOL mode, 33 mW sleep mode
— IEEE 802.3u MII for connecting alternative external Physical Layer Devices

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