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DP83815 View Datasheet(PDF) - National ->Texas Instruments

Part NameDP83815 National-Semiconductor
National ->Texas Instruments National-Semiconductor
Description10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter™)
DP83815 Datasheet PDF : 108 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
1.0 Connection Diagram
1.1 144 LQFP Package (VNG)
SUBGND1
37
RXAVSS1
38
RXAVDD1
39
VREF
40
RESERVED
41
NC
42
NC
43
RXAVSS2
44
TPRDM
45
TPRDP
46
RXAVDD2
47
NC
48
SUBGND2
49
RESERVED
50
TXDVSS
51
TXIOVSS1
52
TPTDM
53
TPTDP
54
TXIOVSS2
55
TXDVDD
56
MACVSS1
57
MACVDD1
58
PMEN/CLKRUNN
59
PCICLK
60
INTAN
61
RSTN
62
GNTN
63
REQN
64
PCIVSS1
65
AD31
66
AD30
67
AD29
68
PCIVDD1
69
AD28
70
AD27
71
AD26
72
Pin1
Identification
DP83815
144 MA2/LED100N
143 MA1/LED10N
142 MA0/LEDACTN
141 MD7
140 MD6
139 MD5
138 MD4/EEDO
137 VDDIO5
136 VSSIO5
135 MD3
134 MD2
133 MD1/CFGDISN
132 MD0
131 MWRN
130
MRDN
129
MCSN
128
EESEL
127
RESERVED
126
SUBGND3
125
MACVDD2
124
MACVSS2
123
PWRGOOD
122
3VAUX
121
AD0
120
AD1
119
AD2
118
AD3
117
PCIVDD5
116
AD4
115
AD5
114
PCIVSS5
113
AD6
112
AD7
111
CBEN0
110
AD8
109
AD9
Order Number DP83815DVNG
See NS Package Number VNG144A
4
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General Description
DP83815 is a single-chip 10/100 Mb/s Ethernet Controller for the PCI bus. It is targeted at low-cost, high volume PC mother boards, adapter cards, and embedded systems. The DP83815 fully implements the V2.2 33 MHz PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83815 can support full duplex 10/100 Mb/s transmission and reception, with minimum interframe gap.
The DP83815 device is an integration of an enhanced version of the National Semiconductor PCI MAC/BIU (Media Access Controller/Bus Interface Unit) and a 3.3V CMOS physical layer interface.

Features
— IEEE 802.3 Compliant, PCI V2.2 MAC/BIU supports traditional data rates of 10 Mb/s Ethernet and 100 Mb/s Fast Ethernet (via internal phy)
— Bus master - burst sizes of up to 128 dwords (512 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1.1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98,
PC99, SecureOn, and OnNow, including directed
packets, Magic Packet, VLAN packets, ARP packets,
pattern match packets, and Phy status change
— Clkrun function for PCI Mobile Design Guide
— Virtual LAN (VLAN) and long frame support
— Support for IEEE 802.3x Full duplex flow control
— Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 512 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns
— Statistics gathered for support of RFC 1213 (MIB II),
RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing
CPU overhead for management
— Internal 2 KB Transmit and 2 KB Receive data FIFOs
— Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Fully integrated IEEE 802.3/802.3u 3.3V CMOS physical layer
— IEEE 802.3 10BASE-T transceiver with integrated filters
— IEEE 802.3u 100BASE-TX transceiver
— Fully integrated ANSI X3.263 compliant TP-PMD physical sublayer with adaptive equalization and Baseline Wander compensation
— IEEE 802.3u Auto-Negotiation - advertised features configurable via EEPROM
— Full Duplex support for 10 and 100 Mb/s data rates
— Single 25 MHz reference clock
— 144-pin LQFP and 160-pin LBGA packages
— Low power 3.3V CMOS design with typical consumption of 561 mW operating, 380 mW during WOL mode, 33 mW sleep mode
— IEEE 802.3u MII for connecting alternative external Physical Layer Devices

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