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DP83815 View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
DP83815 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter™) National-Semiconductor
National ->Texas Instruments National-Semiconductor
DP83815 Datasheet PDF : 108 Pages
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4.0 Register Set (Continued)
4.2.2 Configuration and Media Status Register
This register allows configuration of a variety of device and phy options, and provides phy status information.
Tag: CFG
Offset: 0004h
Size: 32 bits
Access: Read Write
Hard Reset: 00000000h
Soft Reset: 00000000h
Bit
31
30
29
28
27
26-24
23-18
17
16
15-13
12
11
Bit Name
Description
LNKSTS Link Status
Link status of the internal phy. Asserted when link is good. RO
SPEED100 Speed 100 Mb/s
Speed 100 Mb/s indicator for internal phy. Asserted when speed is set or has negotiated to 100 Mb/s.
De-asserted when speed has been set or negotiated to 10 Mb/s. RO
FDUP Full Duplex
Full Duplex indicator for internal phy. Asserted when duplex mode is set or has negotiated to FULL. De-
asserted when duplex mode has been set or negotiated to HALF. RO
POL
10 Mb/s Polarity Indication
Twisted pair polarity indicator for internal phy. Asserted when operating and 10 Mb/s and the polarity has
been detected as reversed. De-asserted when polarity is normal or phy is operating at 100 Mb/s. RO
ANEG_DN Auto-negotiation Done
Auto-negotiation done indicator from internal phy. Asserted when auto-negotiation process has
completed or is not active. RO
unused
PHY_CFG Phy Configuration
Miscellaneous internal phy Power-On-Reset configuration control bits.
PINT_ACEN Phy Interrupt Auto Clear Enable
When set to a 1, this bit allows the phy interrupt source to be automatically cleared whenever the ISR is
read. When this bit is 0, the phy interrupt source must be manually cleared via access of the phy
registers. R/W
PAUSE_ADV Pause Advertise
This bit is loaded from EEPROM at power-up and is used to configure the internal phy to advertise the
capability of 802.3x pause during auto-negotiation. Setting this bit to 1 will cause the pause function to be
advertised if the phy has also been configured to advertise full duplex capability (See ANEG_SEL).
ANEG_SEL Auto-negotiation Select
These bits are loaded from EEPROM at power-up and are used to define the default state of the internal
phy auto-negotiation logic. R/W These bits are encoded as follows:
000 Auto-negotiation disabled, force 10 Mb/s half duplex
010 Auto-negotiation disabled, force 100 Mb/s half duplex
100 Auto-negotiation disabled, force 10 Mb/s full duplex
110 Auto-negotiation disabled, force 100 Mb/s full duplex
001 Auto-negotiation enabled, advertise 10 Mb/s half & full duplex
011 Auto-negotiation enabled, advertise 10/100 Mb/s half duplex
101 Auto-negotiation enabled, advertise 100 Mb/s half & full duplex
111 Auto-negotiation enabled, advertise 10/100 Mb/s half & full duplex
EXT_PHY External Phy Support
Act as a stand-alone MAC. When set, this bit enables the MII and disables the internal Phy (sets bit 9).
R/W
Reserved
42
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