datasheetbank_Logo    Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :

DP83815 View Datasheet(PDF) - National ->Texas Instruments

Part NameDP83815 National-Semiconductor
National ->Texas Instruments National-Semiconductor
Description10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter™)
DP83815 Datasheet PDF : 108 Pages
First Prev 31 32 33 34 35 36 37 38 39 40 Next Last
4.0 Register Set (Continued)
Bit
24-22
21
20
19
18-16
15-8
7-0
Bit Name
Description
AUX_CURRENT Aux_Current
This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function.
If PMEN generation from D3cold is not supported by the function(PMCAP[31]), this field returns a
value of "000b" when read.
Bit
3.3Vaux
24 23 22 Max. Current Required
110
320 mA
000
0 (self powered)
DSI
Device Specific Initialization
This bit is set to 1 to indicate to the system that initialization of the DP83815 device is required
(beyond the standard PCI configuration header) before the generic class device driver is able to use
it. A 1 indicates that DP83815 requires a DSI sequence following transition to the D0 uninitialized
state. This bit can be loaded from the EEPROM.
Reserved
(reads return 0)
PMEC
PME Clock
Returns 0 to indicate PCI clock not needed for PMEN.
PMV
Power Management Version
This bit field indicates compliance to a specific PM specification rev level. Currently set to 010b.
NLIPTR
Next List Item Pointer
Offset into PCI configuration space for the location of the next item in the Capabilities Linked List.
Returns 00h as no other capabilities are offered.
CAPID
Capability ID
Always returns 01h for Power Management ID.
4.1.12 Power Management Control and Status Register
This register contains PM control and status information.
Tag: PMCSR
Size: 32 bits
Offset: 44h
Access: Read Write
Hard Reset: 00000000h
Soft Reset: unchanged
Bit
31-24
23-16
15
14-9
8
7-2
1-0
Bit Name
BSE
PMESTS
PMEEN
PSTATE
Description
Reserved
(reads return 0)
Bridge Support Extensions
unused (reads return 0)
PME Status
Sticky bit which represents the state of the PME logic, regardless of the state of the PMEEN bit.
Reserved
(reads return 0)
PME Enable
When set to 1, this bit enables the assertion of the PME function on the PMEN pin. When 0, the PMEN
pin is forced to be inactive. This value can be loaded from the EEPROM.
Unused
(reads return 0)
Power State
This 2 bit field is used to determine the current power state of DP83815, and to set a new power state.
00 - D0
10 - D2
01 - D1
11 - D3hot/cold
39
www.national.com
Direct download click here
 

General Description
DP83815 is a single-chip 10/100 Mb/s Ethernet Controller for the PCI bus. It is targeted at low-cost, high volume PC mother boards, adapter cards, and embedded systems. The DP83815 fully implements the V2.2 33 MHz PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83815 can support full duplex 10/100 Mb/s transmission and reception, with minimum interframe gap.
The DP83815 device is an integration of an enhanced version of the National Semiconductor PCI MAC/BIU (Media Access Controller/Bus Interface Unit) and a 3.3V CMOS physical layer interface.

Features
— IEEE 802.3 Compliant, PCI V2.2 MAC/BIU supports traditional data rates of 10 Mb/s Ethernet and 100 Mb/s Fast Ethernet (via internal phy)
— Bus master - burst sizes of up to 128 dwords (512 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1.1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98,
PC99, SecureOn, and OnNow, including directed
packets, Magic Packet, VLAN packets, ARP packets,
pattern match packets, and Phy status change
— Clkrun function for PCI Mobile Design Guide
— Virtual LAN (VLAN) and long frame support
— Support for IEEE 802.3x Full duplex flow control
— Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 512 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns
— Statistics gathered for support of RFC 1213 (MIB II),
RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing
CPU overhead for management
— Internal 2 KB Transmit and 2 KB Receive data FIFOs
— Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Fully integrated IEEE 802.3/802.3u 3.3V CMOS physical layer
— IEEE 802.3 10BASE-T transceiver with integrated filters
— IEEE 802.3u 100BASE-TX transceiver
— Fully integrated ANSI X3.263 compliant TP-PMD physical sublayer with adaptive equalization and Baseline Wander compensation
— IEEE 802.3u Auto-Negotiation - advertised features configurable via EEPROM
— Full Duplex support for 10 and 100 Mb/s data rates
— Single 25 MHz reference clock
— 144-pin LQFP and 160-pin LBGA packages
— Low power 3.3V CMOS design with typical consumption of 561 mW operating, 380 mW during WOL mode, 33 mW sleep mode
— IEEE 802.3u MII for connecting alternative external Physical Layer Devices

Share Link : National-Semiconductor
All Rights Reserved © datasheetbank.com 2014 - 2018 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]