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DP83815 View Datasheet(PDF) - National ->Texas Instruments

Part NameDP83815 National-Semiconductor
National ->Texas Instruments National-Semiconductor
Description10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter™)
DP83815 Datasheet PDF : 108 Pages
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4.0 Register Set (Continued)
Bit
Bit Name
Description
6
PERRSP Parity Error Response
When set, DP83815 will assert PERRN on the detection of a data parity error when acting as the target,
and will sample PERRN when acting as the initiator. Also, setting PERRSP allows SERREN to enable
the assertion of SERRN. When reset, all address and data parity errors are ignored and neither SERRN
nor PERRN are asserted.
5-3
Unused
(reads return 0)
2
BMEN Bus Master Enable
When set, DP83815 is allowed to act as a PCI bus master. When reset, DP83815 is prohibited from
acting as a PCI bus master.
1
MSEN Memory Space Address
When set, DP83815 responds to memory space accesses. When reset, DP83815 ignores memory
space accesses.
0
I/OSEN I/O Space Access
When set, DP83815 responds to I/O space accesses. When reset, DP83815 ignores I/O space
accesses.
4.1.3 Configuration Revision ID Register
This register stores the silicon revision number, revision number of software interface specification and lets the
configuration software know that it is an Ethernet controller in the class of network controllers.
Tag: CFGRID
Offset: 08h
Size: 32 bits
Access: Read Only
Hard Reset: 02000000h
Soft Reset: Unchanged
Bit
31-24
23-16
15-8
7-0
Bit Name
BASECL
SUBCL
PROGIF
REVID
Description
Base Class
Returns 02h which specifies a network controller.
Sub Class
Returns 00h which specifies an Ethernet controller.
Programming IF
Returns 00h which specifies the first release of the DP83815 Software Interface Specification.
Silicon Revision
Returns 00h which specifies the silicon revision.
34
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General Description
DP83815 is a single-chip 10/100 Mb/s Ethernet Controller for the PCI bus. It is targeted at low-cost, high volume PC mother boards, adapter cards, and embedded systems. The DP83815 fully implements the V2.2 33 MHz PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83815 can support full duplex 10/100 Mb/s transmission and reception, with minimum interframe gap.
The DP83815 device is an integration of an enhanced version of the National Semiconductor PCI MAC/BIU (Media Access Controller/Bus Interface Unit) and a 3.3V CMOS physical layer interface.

Features
— IEEE 802.3 Compliant, PCI V2.2 MAC/BIU supports traditional data rates of 10 Mb/s Ethernet and 100 Mb/s Fast Ethernet (via internal phy)
— Bus master - burst sizes of up to 128 dwords (512 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1.1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98,
PC99, SecureOn, and OnNow, including directed
packets, Magic Packet, VLAN packets, ARP packets,
pattern match packets, and Phy status change
— Clkrun function for PCI Mobile Design Guide
— Virtual LAN (VLAN) and long frame support
— Support for IEEE 802.3x Full duplex flow control
— Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 512 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns
— Statistics gathered for support of RFC 1213 (MIB II),
RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing
CPU overhead for management
— Internal 2 KB Transmit and 2 KB Receive data FIFOs
— Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Fully integrated IEEE 802.3/802.3u 3.3V CMOS physical layer
— IEEE 802.3 10BASE-T transceiver with integrated filters
— IEEE 802.3u 100BASE-TX transceiver
— Fully integrated ANSI X3.263 compliant TP-PMD physical sublayer with adaptive equalization and Baseline Wander compensation
— IEEE 802.3u Auto-Negotiation - advertised features configurable via EEPROM
— Full Duplex support for 10 and 100 Mb/s data rates
— Single 25 MHz reference clock
— 144-pin LQFP and 160-pin LBGA packages
— Low power 3.3V CMOS design with typical consumption of 561 mW operating, 380 mW during WOL mode, 33 mW sleep mode
— IEEE 802.3u MII for connecting alternative external Physical Layer Devices

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