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DP83815 View Datasheet(PDF) - National ->Texas Instruments

Part NameDP83815 National-Semiconductor
National ->Texas Instruments National-Semiconductor
Description10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter™)
DP83815 Datasheet PDF : 108 Pages
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3.0 Functional Description (Continued)
Figure 3-9 100BASE-TX BLW Event Diagram
3.10.3 Digital Adaptive Equalization
When transmitting data at high speeds over copper twisted
pair cable, frequency dependent attenuation becomes a
concern. In high-speed twisted pair signalling, the
frequency content of the transmitted signal can vary greatly
during normal operation based primarily on the
randomness of the scrambled data stream. This variation
in signal attenuation caused by frequency variations must
be compensated for to ensure the integrity of the
transmission.
In order to ensure quality transmission when employing
MLT-3 encoding, the compensation must be able to adapt
to various cable lengths and cable types depending on the
installed environment. The selection of long cable lengths
for a given implementation, requires significant
compensation which will over-compensate for shorter, less
attenuating lengths. Conversely, the selection of short or
intermediate cable lengths requiring less compensation will
cause serious under-compensation for longer length
cables. Therefore, the compensation or equalization must
be adaptive to ensure proper conditioning of the received
signal independent of the cable length.
The DP83815 utilizes an extremely robust equalization
scheme referred to herein as ‘Digital Adaptive
Equalization’. Traditional designs use a pseudo adaptive
equalization scheme that determines the approximate
cable length by monitoring signal attenuation at certain
frequencies. This attenuation value was compared to the
internal receive input reference voltage. This comparison
would indicate the amount of equalization to use. Although
this scheme is used successfully on the DP83223V twister,
it is sensitive to transformer mismatch, resistor variation
and process induced offset. The DP83223V also required
an external attenuation network to help match the incoming
signal amplitude to the internal reference.
The Digital Equalizer removes ISI (Inter Symbol
Interference) from the receive data stream by continuously
adapting to provide a filter with the inverse frequency
response of the channel. When used in conjunction with a
gain stage, this enables the receive 'eye pattern' to be
opened sufficiently to allow very reliable data recovery.
Traditionally 'adaptive' equalizers selected 1 of N filters in
an attempt to match the cables characteristics. This
approach will typically leave holes at certain cable lengths,
where the performance of the equalizer is not optimized.
The DP83815 equalizer is truly adaptive.
The curves given in Figure 3-10 illustrate attenuation at
certain frequencies for given cable lengths. This is derived
from the worst case frequency vs. attenuation figures as
specified in the EIA/TIA Bulletin TSB-36. These curves
indicate the significant variations in signal attenuation that
must be compensated for by the receive adaptive
equalization circuit.
Figure 3-11 represents a scrambled IDLE transmitted over
zero meters of cable as measured at the AII (Active Input
Interface) of the receiver. Figure 3-12 and Figure 3-13
represent the signal degradation over 50 and 100 meters
of category V cable respectively, also measured at the AII.
These plots show the extreme degradation of signal
integrity and indicate the requirement for a robust adaptive
equalizer.
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General Description
DP83815 is a single-chip 10/100 Mb/s Ethernet Controller for the PCI bus. It is targeted at low-cost, high volume PC mother boards, adapter cards, and embedded systems. The DP83815 fully implements the V2.2 33 MHz PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83815 can support full duplex 10/100 Mb/s transmission and reception, with minimum interframe gap.
The DP83815 device is an integration of an enhanced version of the National Semiconductor PCI MAC/BIU (Media Access Controller/Bus Interface Unit) and a 3.3V CMOS physical layer interface.

Features
— IEEE 802.3 Compliant, PCI V2.2 MAC/BIU supports traditional data rates of 10 Mb/s Ethernet and 100 Mb/s Fast Ethernet (via internal phy)
— Bus master - burst sizes of up to 128 dwords (512 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1.1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98,
PC99, SecureOn, and OnNow, including directed
packets, Magic Packet, VLAN packets, ARP packets,
pattern match packets, and Phy status change
— Clkrun function for PCI Mobile Design Guide
— Virtual LAN (VLAN) and long frame support
— Support for IEEE 802.3x Full duplex flow control
— Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 512 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns
— Statistics gathered for support of RFC 1213 (MIB II),
RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing
CPU overhead for management
— Internal 2 KB Transmit and 2 KB Receive data FIFOs
— Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Fully integrated IEEE 802.3/802.3u 3.3V CMOS physical layer
— IEEE 802.3 10BASE-T transceiver with integrated filters
— IEEE 802.3u 100BASE-TX transceiver
— Fully integrated ANSI X3.263 compliant TP-PMD physical sublayer with adaptive equalization and Baseline Wander compensation
— IEEE 802.3u Auto-Negotiation - advertised features configurable via EEPROM
— Full Duplex support for 10 and 100 Mb/s data rates
— Single 25 MHz reference clock
— 144-pin LQFP and 160-pin LBGA packages
— Low power 3.3V CMOS design with typical consumption of 561 mW operating, 380 mW during WOL mode, 33 mW sleep mode
— IEEE 802.3u MII for connecting alternative external Physical Layer Devices

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