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DP83815 View Datasheet(PDF) - National ->Texas Instruments

Part NameDP83815 National-Semiconductor
National ->Texas Instruments National-Semiconductor
Description10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter™)
DP83815 Datasheet PDF : 108 Pages
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3.0 Functional Description (Continued)
3.3.2 Boot PROM
PA SFD DA SA LEN Data
FCS
The BIOS ROM interface allows the DP83815 to read from
and write data to an external ROM/Flash device.
3.3.3 EEPROM
60b 4b 6B 6B 2B 46B-1500B 4B
Note: B = Bytes
b = bits
Figure 3-3 Ethernet Packet Format
3.2.4 MIB
The MIB block contains counters to track certain media
events required by the management specifications RFC
1213 (MIB II), RFC 1398 (Ether-like MIB), and IEEE 802.3
LME. The counters provided are for events which are either
difficult or impossible to be intercepted directly by software.
Not all counters are implemented, however required
counters can be calculated from the counters provided.
3.3 Interface Definitions
3.3.1 PCI System Bus
This interface allows direct connection of the DP83815 to a
33 MHz PCI system bus. The DP83815 supports zero wait
state data transfers with burst sizes up to 128 dwords. The
DP83815 conforms to 3.3V AC/DC specifications, but has
5V tolerant inputs.
The DP83815 supports the attachment of an external
EEPROM. The EEPROM interface provides the ability for
the DP83815 to read from and write data to an external
serial EEPROM device. The DP83815 will auto-load values
from the EEPROM to certain fields in PCI configuration
space and operational space and perform a checksum to
verify that the data is valid. Values in the external EEPROM
allow default fields in PCI configuration space and I/O
space to be overridden following a hardware reset. If the
EEPROM is not present, the DP83815 initialization uses
default values for the appropriate Configuration and
Operational Registers. Software can read and write to the
EEPROM using “bit-bang” accesses via the EEPROM
Access Register (MEAR).
3.3.4 Clock
The clock interface provides the 25 MHz clock reference
input for the DP83815 IC. The X1 and X2 pin capacitances
are 4.5 + 1.0pF. The X1 input signal amplitude should be
approximately 1V. This interface supports operation from a
25 MHz, 50 ppm CMOS oscillator, or a 25 MHz, 50 ppm,
parallel, 20 pF load, < 40 ESR crystal resonator. A 20pF
crystal resonator would require C1 and C2 load capacitors
of 27-33pF each.
16
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General Description
DP83815 is a single-chip 10/100 Mb/s Ethernet Controller for the PCI bus. It is targeted at low-cost, high volume PC mother boards, adapter cards, and embedded systems. The DP83815 fully implements the V2.2 33 MHz PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83815 can support full duplex 10/100 Mb/s transmission and reception, with minimum interframe gap.
The DP83815 device is an integration of an enhanced version of the National Semiconductor PCI MAC/BIU (Media Access Controller/Bus Interface Unit) and a 3.3V CMOS physical layer interface.

Features
— IEEE 802.3 Compliant, PCI V2.2 MAC/BIU supports traditional data rates of 10 Mb/s Ethernet and 100 Mb/s Fast Ethernet (via internal phy)
— Bus master - burst sizes of up to 128 dwords (512 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1.1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98,
PC99, SecureOn, and OnNow, including directed
packets, Magic Packet, VLAN packets, ARP packets,
pattern match packets, and Phy status change
— Clkrun function for PCI Mobile Design Guide
— Virtual LAN (VLAN) and long frame support
— Support for IEEE 802.3x Full duplex flow control
— Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 512 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns
— Statistics gathered for support of RFC 1213 (MIB II),
RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing
CPU overhead for management
— Internal 2 KB Transmit and 2 KB Receive data FIFOs
— Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Fully integrated IEEE 802.3/802.3u 3.3V CMOS physical layer
— IEEE 802.3 10BASE-T transceiver with integrated filters
— IEEE 802.3u 100BASE-TX transceiver
— Fully integrated ANSI X3.263 compliant TP-PMD physical sublayer with adaptive equalization and Baseline Wander compensation
— IEEE 802.3u Auto-Negotiation - advertised features configurable via EEPROM
— Full Duplex support for 10 and 100 Mb/s data rates
— Single 25 MHz reference clock
— 144-pin LQFP and 160-pin LBGA packages
— Low power 3.3V CMOS design with typical consumption of 561 mW operating, 380 mW during WOL mode, 33 mW sleep mode
— IEEE 802.3u MII for connecting alternative external Physical Layer Devices

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