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ADC0800PCD View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
ADC0800PCD 8-Bit A/D converter National-Semiconductor
National ->Texas Instruments National-Semiconductor
ADC0800PCD Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Application Hints (Continued)
CMOS will satisfy this requirement but a pull-up resistor
should be used for TTL logic inputs
The EOC line (pin 9) will be in the low state for a maximum
of 40 clock periods to indicate ‘‘busy’’ A START pulse that
occurs while the A D is BUSY will reset the SAR and start a
new conversion with the EOC signal remaining in the low
state until the end of this new conversion When the conver-
sion is complete the EOC line will go to the high voltage
state An additional 4 clock periods must be allowed to
elapse after EOC goes high before a new conversion cycle
is requested Start Conversion pulses that occur during this
last 4 clock period interval may be ignored (see Figure 1 and
2 for high speed operation) This is a problem only for high
conversion rates and keeping the number of conversions
per second less than fCLOCK 44 automatically guarantees
proper operation For example for an 800 kHz clock ap-
proximately 18 000 conversions per second are allowed
The transfer of the new digital data to the output is initiated
when EOC goes to the high voltage state
Standard supplies are VSSe a5V VGGeb12V and
VDDe0V Device accuracy is dependent on stability of the
reference voltage and has slight sensitivity to VSS VGG
VDD has no effect on accuracy Noise spikes on the VSS
and VGG supplies can cause improper conversion there-
fore filtering each supply with a 4 7 mF tantalum capacitor is
Simply tying the EOC output to the Start Conversion input
will allow continuous conversions but an oscillation on this
line will exist during the first 4 clock periods after EOC goes
high Adding a D flip-flop between EOC (D input) to Start
Conversion (Q output) will prevent the oscillation and will
allow a stop continuous control via the ‘‘clear’’ input
To prevent missing a start pulse that may occur after EOC
goes high and prior to the required 4 clock period time inter-
val the circuit of Figure 1 can be used The RS latch can be
set at any time and the 4-stage shift register delays the
application of the start pulse to the A D by 4 clock periods
The RS latch is reset 1 clock period after the A D EOC
signal goes to the low voltage state This circuit also pro-
vides a Start Conversion pulse to the A D which is 1 clock
period wide
A second control logic application circuit is shown in Figure
2 This allows an asynchronous start pulse of arbitrary
length less than TC to continuously convert for a fixed high
level and provides a single clock period start pulse to the
A D The binary counter is loaded with a count of 11 when
the start pulse to the A D appears Counting is inhibited
until the EOC signal from the A D goes high A carry pulse
is then generated 4 clock periods after EOC goes high and
is used to reset the input RS latch This carry pulse can be
used to indicate that the conversion is complete the data
has transferred to the output buffers and the system is
ready for a new conversion cycle
FIGURE 1 Delaying an Asynchronous Start Pulse
TL H 5670 – 3
FIGURE 2 A D Control Logic
TL H 5670 – 10
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