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AD9057-80 Просмотр технического описания (PDF) - Analog Devices

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AD9057-80 8-Bit 40 MSPS/60 MSPS/80 MSPS A/D Converter ADI
Analog Devices ADI
AD9057-80 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AD9057
Parameter
Test
Temp Level
AD9057BRS-40
AD9057BRS-60
AD9057BRS-80
Min Typ Max Min Typ Max Min Typ Max Unit
DIGITAL OUTPUTS
Logic 1 Voltage (VDD = 3 V)
Logic 1 Voltage (VDD = 5 V)
Logic 0 Voltage
Output Coding
Full VI
Full IV
Full VI
2.95
2.95
2.95
V
4.95
4.95
4.95
V
0.05
0.05
0.05 V
Offset Binary Code Offset Binary Code Offset Binary Code
POWER SUPPLY
VD Supply Current (VD = 5 V)
VDD Supply Current (VDD = 3 V)4
Power Dissipation5, 6
Power-Down Dissipation
Power Supply Rejection Ratio
(PSRR)
Full VI
Full VI
Full VI
Full VI
25C V
36 48
4.0 6.5
192 260
6
10
3
38 48
5.5 6.5
205 260
6
10
3
40 51 mA
7.4 8.8 mA
220 281 mW
6
10 mW
3
mV/V
NOTES
1Gain error and gain temperature coefficient are based on the ADC only (with a fixed 2.5 V external reference).
2tV and tPD are measured from the 1.5 V level of the encode to the 10%/90% levels of the digital output swing. The digital output load during test is not to exceed
an ac load of 10 pF or a dc current of ± 40 mA.
3SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 1.0 V full-scale input range.
4Digital supply current based on VDD = 3 V output drive with <10 pF loading under dynamic test conditions.
5Power dissipation is based on specified encode and 10.3 MHz analog input dynamic test conditions (V D = 5 V ± 5%, VDD = 3 V ± 5%).
6Typical thermal impedance for the RS style (SSOP) 20-lead package : qJC = 46C/W, qCA = 80C/W, and qJA = 126C/W.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level Description
I
100% production tested.
II
100% production tested at 25C and sample
tested at specified temperatures.
III
Sample tested only.
IV
Parameter is guaranteed by design and charac-
terization testing.
V
Parameter is a typical value only.
VI
100% production tested at 25C; guaranteed
by design and characterization testing
for industrial temperature range.
N
AIN
ENCODE
tA
tEH
N+1
N+2
N+3
N+4
N+5
tEL
DIGITAL
OUTPUTS
N–3
N–2
N–1
tV
N
tPD
N+1
N+2
MIN TYP MAX
tA APERTURE DELAY
2.7 ns
tEH PULSEWIDTH HIGH
166 ns
tEL PULSEWIDTH LOW
166 ns
tV OUTPUT VALID TIME 4.0 ns 6.6 ns
tPD OUTPUT PROP DELAY
9.5 ns
Figure 1. Timing Diagram
REV. D
–3–
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