Min Typ Max Min Typ Max Min Typ Max Unit
Logic 1 Voltage (VDD = 3 V)
Logic 1 Voltage (VDD = 5 V)
Logic 0 Voltage
Offset Binary Code Offset Binary Code Offset Binary Code
VD Supply Current (VD = 5 V)
VDD Supply Current (VDD = 3 V)4
Power Dissipation5, 6
Power Supply Rejection Ratio
40 51 mA
7.4 8.8 mA
220 281 mW
1Gain error and gain temperature coefficient are based on the ADC only (with a fixed 2.5 V external reference).
2tV and tPD are measured from the 1.5 V level of the encode to the 10%/90% levels of the digital output swing. The digital output load during test is not to exceed
an ac load of 10 pF or a dc current of ± 40 mA.
3SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 1.0 V full-scale input range.
4Digital supply current based on VDD = 3 V output drive with <10 pF loading under dynamic test conditions.
5Power dissipation is based on specified encode and 10.3 MHz analog input dynamic test conditions (V D = 5 V ± 5%, VDD = 3 V ± 5%).
6Typical thermal impedance for the RS style (SSOP) 20-lead package : qJC = 46∞C/W, qCA = 80∞C/W, and qJA = 126∞C/W.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level Description
100% production tested.
100% production tested at 25∞C and sample
tested at specified temperatures.
Sample tested only.
Parameter is guaranteed by design and charac-
Parameter is a typical value only.
100% production tested at 25∞C; guaranteed
by design and characterization testing
for industrial temperature range.
MIN TYP MAX
tA APERTURE DELAY
tEH PULSEWIDTH HIGH
tEL PULSEWIDTH LOW
tV OUTPUT VALID TIME 4.0 ns 6.6 ns
tPD OUTPUT PROP DELAY
Figure 1. Timing Diagram