AD8180 View Datasheet(PDF) - Analog Devices
Part Name
Description
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AD8180 Datasheet PDF : 12 Pages
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AD8180/AD8182
NOTES
1ENABLE pin is grounded. IN0 = +1 V dc, IN1 = –1 V dc. SELECT input is driven with 0 V to +5 V pulse. Measure transition time from 50% of the SELECT input value
(+2.5 V) and 10% (or 90%) of the total output voltage transition from IN0 channel voltage (+1 V) to IN1 (–1 V), or vice versa.
2ENABLE pin is driven with 0 V to +5 V pulse (with 3 ns edges). State of SELECT input determines which channel is activated (i.e., if SELECT = Logic 0, IN0 is selected). Set
IN0 = +1 V dc, IN1 = –1 V dc, and measure transition time from 50% of ENABLE pulse (+2.5 V) to 90% of the total output voltage change. In Figure 5, ∆tOFF is the disable
time, ∆tON is the enable time.
3All inputs are grounded. SELECT input is driven with 0 V to +5 V pulse. The outputs are monitored. Speeding the edges of the SELECT pulse increases the glitch magnitude
due to coupling via the ground plane. Removing the SELECT input termination will lower glitch, as does increasing RL.
4Decreasing RL lowers the bandwidth slightly. Increasing CL lowers the bandwidth considerably (see Figure 19).
5A resistor (RS) placed in series with the mux inputs serves to optimize 0.1 dB flatness, but is not required. Increasing output capacitance will increase peaking and reduce band-
width (see Figure 20.)
6Select input which is not being driven (i.e., if SELECT is Logic 1, input activated is IN1); drive all other inputs with VIN = 0.707 V rms and monitor output at ƒ = 5 and 30 MHz.
RL = 1 kΩ (see Figure 13).
7Mux is disabled (i.e., ENABLE = Logic 1) and all inputs are driven simultaneously with VIN = 0.446 V rms. Output is monitored at ƒ = 5 and 30 MHz. RL = 30 Ω to simulate
RON of one enabled mux within a system (see Figure 14). In this mode the output impedance is very high (typ 10 M Ω), and the signal couples across the package; the load imped-
ance determines the crosstalk.
8Voltage gain decreases for lower values of RL. The resistive divider formed by the mux enabled output resistance (27 Ω) and RL causes a gain which decreases as RL decreases
(i.e., the voltage gain is approximately 0.97 V/V (3% gain error) for RL = 1 kΩ).
9Larger values of RL provide wider output voltage swings, as well as better gain accuracy. See Note 8.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
While the AD8180 and AD8182 are internally short circuit
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Internal Power Dissipation2
AD8180 8-Lead Plastic DIP (N) . . . . . . . . . . . . . . . . 1.3 Watts
protected, this may not be sufficient to guarantee that the maxi-
mum junction temperature (+150°C) is not exceeded under all
conditions. To ensure proper operation, it is necessary to observe
AD8180 8-Lead Small Outline (R) . . . . . . . . . . . . . . 0.9 Watts the maximum power derating curves shown in Figures 2 and 3.
AD8182 14-Lead Plastic DIP (N) . . . . . . . . . . . . . . . 1.6 Watts
AD8182 14-Lead Small Outline (R) . . . . . . . . . . . . . 1.0 Watts
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Output Short Circuit Duration . . . . . Observe Power Derating Curves
Storage Temperature Range
2.0
8-LEAD PLASTIC DIP PACKAGE
TJ = +150؇C
1.5
N and R Package . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . +300°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air: 8-Lead Plastic DIP Package: θJA = 90°C/W;
8-Lead SOIC Package: θJA = 155°C/W; 14-Lead Plastic Package: θJA = 75°C/W;
14-Lead SOIC Package: θJA = 120°C/W, where PD = (TJ–TA)/θJA.
ORDERING GUIDE
1.0
8-LEAD SOIC PACKAGE
0.5
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – ؇C
Model
Temperature Package
Range
Description
Package
Option
AD8180AN
–40°C to +85°C 8-Lead Plastic DIP N-8
AD8180AR
–40°C to +85°C 8-Lead SOIC
SO-8
AD8180AR-REEL –40°C to +85°C 13" Reel SOIC
SO-8
AD8180AR-REEL7 –40°C to +85°C 7" Reel SOIC
SO-8
AD8182AN
–40°C to +85°C 14-Lead Plastic DIP N-14
AD8182AR
–40°C to +85°C 14-Lead Narrow SOIC R-14
AD8182AR-REEL –40°C to +85°C 13" Reel SOIC
R-14
AD8182AR-REEL7 –40°C to +85°C 7" Reel SOIC
R-14
AD8180-EB
Evaluation Board
AD8182-EB
Evaluation Board
Figure 2. AD8180 Maximum Power Dissipation vs.
Temperature
2.5
TJ = +150؇C
2.0
14-LEAD
PLASTIC DIP PACKAGE
1.5
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8180 and AD8182 is limited by the associated rise in junc-
tion temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass transition
temperature of the plastic, approximately +150°C. Exceeding
this limit temporarily may cause a shift in parametric perfor-
mance due to a change in the stresses exerted on the die by the
package. Exceeding a junction temperature of +175°C for an
extended period can result in device failure.
14-LEAD SOIC
1.0
0.5
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – ؇C
Figure 3. AD8182 Maximum Power Dissipation vs.
Temperature
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8180/AD8182 feature proprietary ESD protection circuitry, permanent damage
WARNING!
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ESD SENSITIVE DEVICE
REV. B
–3–
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