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BS62LV1024DC View Datasheet(PDF) - Brilliance Semiconductor

Part Name
Description
View to exact match
BS62LV1024DC
BSI
Brilliance Semiconductor BSI
BS62LV1024DC Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
BSI Very Low Power/Voltage CMOS SRAM
128K X 8 bit
BS62LV1024
„ FEATURES
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.02uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
„ PRODUCT FAMILY
„ DESCRIPTION
The BS62LV1024 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.02uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV1024 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV1024 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP, 8mmx13.4mm
STSOP and 8mmx20mm TSOP.
PRODUCT
FA M ILY
O P E R ATIN G
Vcc
TE M P E R ATU R E R A N G E
B S 6 2 LV 1 0 2 4 S C
B S 6 2 LV 1 0 2 4 T C
B S 6 2 LV 1 0 2 4 S T C
B S 6 2 LV 1 0 2 4 P C
B S 6 2 LV 1 0 2 4J C
B S 6 2 LV 1 0 2 4 D C
B S 6 2 LV 1 0 2 4 S I
B S 6 2 LV 1 0 2 4 T I
B S 6 2 LV 1 0 2 4 S TI
B S 6 2 LV 1 0 2 4 P I
B S 6 2 LV 1 0 2 4J I
B S 6 2 LV 1 0 2 4 D I
+0OC to +70 OC 2.4V ~ 5.5V
-40OC to +85 OC 2.4V ~ 5.5V
SPEED
(ns)
Vcc=3V
70
70
P O W E R D IS SIPATIO N
S ta n d b y
O perating
(IccS B 1, M ax)
(Icc, M ax)
Vcc=5V Vcc=3V Vcc=5V Vcc=3V
3.0uA
1.0uA 35m A 20m A
5.0uA
1.5uA 40m A 25m A
PKG TYPE
SO P-32
TSO P-32
STSO P-32
PD IP-32
SO J-32
D IC E
SO P-32
TSO P-32
STSO P-32
PD IP-32
SO J-32
D IC E
„ PIN CONFIGURATIONS
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
32
2
31
3
30
4
29
5
28
6 BS62LV1024SC 27
7 BS62LV1024SI 26
8
9
BS62LV1024PC
BS62LV1024PI
25
BS62LV1024JC 24
10 BS62LV1024JI 23
11
22
12
21
13
20
14
19
15
18
16
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
A11 1
A9 2
A8 3
A13 4
WE 5
CE2 6
A15 7
VCC 8
NC 9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
BS62LV1024TC
BS62LV1024STC
BS62LV1024TI
BS62LV1024STI
32 OE
31 A10
30 CE1
29 DQ7
28 DQ6
27 DQ5
26 DQ4
25 DQ3
24 GND
23 DQ2
22 DQ1
21 DQ0
20 A0
19 A1
18 A2
17 A3
„ BLOCK DIAGRAM
A6
A7
A12
A14
A16
A15
A13
A8
A9
A11
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE2
CE1
WE
OE
Vdd
Gnd
Address
20
Input
Buffer
Row
Decoder
1024
Memory Array
1024 x 1024
8
8
Control
Data
Input
Buffer
Data
Output
Buffer
1024
8
Column I/O
Write Driver
Sense Amp
8
128
Column Decoder
14
Address Input Buffer
A5 A4 A3 A2 A1 A0 A10
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS62LV1024
1
Revision 2.2
April 2001
 

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