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NM93C06L View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
NM93C06L 256-/1024-/2048-/4096-Bit Serial EEPROM with Extended Voltage (2.7V to 5.5V)(MICROWIRETM Bus Interface) National-Semiconductor
National ->Texas Instruments National-Semiconductor
NM93C06L Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Capacitance (Note 3)
TA e 25 C f e 1 MHz
Symbol
Test
Typ Max Units
COUT
Output Capacitance
5
pF
CIN
Input Capacitance
5
pF
Note 1 Stress above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device This is a stress rating only and operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied Exposure to absolute maximum rating
conditions for extended periods may affect device reliability
Note 2 CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal device registers (device reset) prior to beginning another
opcode cycle (this is shown in the opcode diagrams in the following pages)
Note 3 This parameter is periodically sampled and not 100% tested
Note 4 Typical leakage values are in the 20 nA range
Note 5 The shortest allowable SK clock period e 1 fSK (as shown under the fSK parameter) Maximum SK clock speed (minimum SK period) is determined by the
interaction of several AC parameters stated in the datasheet Within this SK period both tSKH and tSKL limits must be observed Therefore it is not allowable to set
1 tSK e tSKH (minimum) a tSKL (minimum) for shorter SK cycle time operation
AC Test Conditions
VCC Range
2 7V s VCC k 4 5V
(Extended Voltage Levels)
4 5V s VCC s 5 5V
(TTL Levels)
VIL VIH
Input Levels
0 3V 1 8V
VIL VIH
Timing Levels
1 0V
VOL VOH
Timing Levels
0 8V 1 5V
0 4V 2 4V
1 0V 2 0V
0 4V 2 4V
Output Load 1 TTL Gate (CL e 100 pF)
IOL IOH
g10 mA
b2 1 mA 0 4 mA
Functional Description
The NM93C06L C46L C56L C66L device have 7 instruc-
tions as described below Note that the MSB of any instruc-
tion is a ‘‘1’’ and is viewed as a start bit in the interface
sequence For the C06 and C46 the next 8 bits carry the op
code and the 6-bit address for register selection For the
C56 and C66 the next 10-bits carry the op code and the 8-
bit address for register selection
Read (READ)
The READ instruction outputs serial data on the DO pin
After a READ instruction is received the instruction and ad-
dress are decoded followed by data transfer from the se-
lected memory register into a 16-bit serial-out shift register
A dummy bit (logical 0) precedes the 16-bit data output
string Output data changes are initiated by a low to high
transition of the SK clock
Erase Write Enable (WEN)
When VCC is applied to the part it powers up in the Erase
Write Disable (WDS) state Therefore all programming
modes must be preceded by an Erase Write Enable WEN
instruction Once an Erase Write Enable instruction is exe-
cuted programming remains enabled until an Erase Write
Disable (WDS) instruction is executed or VCC is completely
removed from the part
Erase (ERASE)
The ERASE instruction will program all bits in the selected
register to the logical ‘‘1’’ state CS is brought low following
the loading of the last address bit This falling edge of the
CS pin initiates the self-timed programming cycle
The DO pin indicates the READY BUSY status of the chip if
CS is brought high after the tCS interval DO e logical ‘‘0’’
indicates that programming is still in progress DO e logical
‘‘1’’ indicates that the register at the address specified in
the instruction has been erased and the part is ready for
another instruction
5
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