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NM25C040 View Datasheet(PDF) - Fairchild Semiconductor

Part NameDescriptionManufacturer
NM25C040 4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus) Fairchild
Fairchild Semiconductor Fairchild
NM25C040 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Functional Description (Continued)
TABLE 3. Block Write Protection Levels
READ SEQUENCE: Reading the memory via the serial SPI link
Level
Status Register Bits
Array
requires the following sequence. The CS line is pulled low to select
the device. The READ op-code (which includes A8) is transmitted
Address
BP1
BP0
Protected
on the SI line followed by the byte address (A7–A0) to be read.
0
0
0
None
After this is done, data on the SI line becomes don’t care. The data
1
0
1
180-1FF
(D7–D0) at the address specified is then shifted out on the SO line.
If only one byte is to be read, the CS line can be pulled back to the
2
1
0
100-1FF
high level. It is possible to continue the READ sequence as the
byte adress is automatically incremented and data will continue to
3
1
1
000-1FF
be shifted out. When the highest address is reached (1FF), the
address counter rolls over to lowest address (000) allowing the WRITE ENABLE (WREN): When VCC is applied to the chip, it
entire memory to be read in one continuous READ cycle. See “powers up” in the write disable state. Therefore, all programming
Figure 6.
modes must be preceded by a WRITE ENABLE (WREN) instruc-
tion. At the completion of a WRITE or WRSR cycle the device is
 FIGURE 6. Read Sequence
CS
Read Byte
SI
Op-Code Addr.
automatically returned to the write disable state. Note that a
WRITE DISABLE (WRDI) instruction will also return the device to
the write disable state. See Figure 8.
FIGURE 8. Write Enable
CS
SO
Data Data Data Data
SI
n
n+1
n+2
n+3
DS012401-8
READ STATUS REGISTER (RDSR) : The Read Status Register
SO
WREN Op-Code
(RDSR) instruction provides access to the status register is used
DS012401-10
to interrogate the READY/BUSY and WRITE ENABLE status of WRITE DISABLE (WRDI): To protect against accidental data
the chip. Two non-volatile status register bits are used to select disturbance the WRITE DISABLE (WRDI) instruction disables all
one of four levels of BLOCK WRITE PROTECTION. The status programming modes. See Figure 9.
register format is shown in Table 2.
TABLE 2. Status Register Format
Bit Bit Bit Bit Bit Bit Bit Bit
7
65
43
210
X
X
X
X BP1 BP0 WEN RDY
X = Don't Care.
Status register Bit 0 = 0 (RDY) indicates that the device is READY;
Bit 0 = 1 indicates that a program cycle is in progress. Bit 1 = 0
(WEN) indicates that the device is not WRITE ENABLED; Bit 1 =
 FIGURE 9. Write Disable
CS
SI
WRDI Op-Code
SO
DS012401-11
1 indicates that the device is WRITE ENABLED. Non-volatile
status register Bits 2 and 3 (BP0 and BP1) indicate the level of
BLOCK WRITE PROTECTION selected. The block write protec-
tion levels and corresponding status register control bits are
shown in Table 3. Note that if a RDSR instruction is executed
during a programming cycle only the RDY bit is valid. All
other bits are 1s. See Figure 7.
WRITE SEQUENCE: To program the device, the WRITE PRO-
TECT (WP) pin must be held high and two separate instructions
must be executed. The chip must first be write enabled via the
WRITE ENABLE instruction and then a WRITE instruction must
be executed. Moreover, the address of the memory location(s) to
be programmed must be outside the protected address field
selected by the Block Write Protection Level. See Table 3.
 FIGURE 7. Read Status
CS
RDSR
SI
Op-Code
SO
SR Data
MSB…LSB
A WRITE command requires the following sequence. The CS line
is pulled low to select the device, then the WRITE op-code (which
includes A8) is transmitted on the SI line followed by the high order
address byte (A10-A8) and the byte address(A7–A0) and the
corresponding data (D7-D0) to be written. Programming will start
after the CS pin is forced back to a high level. Note that the LOW
to HIGH transition of the CS pin must occur during the SCK low time
immediately after clocking in the D0 data bit. See Figure 10.
DS012401-9
NM25C040 Rev. D.1
7
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