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NM25C040 View Datasheet(PDF) - Fairchild Semiconductor

Part NameDescriptionManufacturer
NM25C040 4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus) Fairchild
Fairchild Semiconductor Fairchild
NM25C040 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
March 1999
NM25C040
4K-Bit Serial CMOS EEPROM
(Serial Peripheral Interface (SPI) Synchronous Bus)
General Description
The NM25C040 is a 4096-bit CMOS EEPROM with an SPI
compatible serial interface. The NM25C040 is designed for data
storage in applications requiring both non-volatile memory and in-
system data updates. This EEPROM is well suited for applications
using the 68HC11 series of microcontrollers that support the SPI
interface for high speed communication with peripheral devices
via a serial bus to reduce pin count. The NM25C040 is imple-
mented in Fairchild Semiconductor’s floating gate CMOS process
that provides superior endurance and data retention.
The serial data transmission of this device requires four signal
lines to control the device operation: Chip Select (CS), Clock
(SCK), Data In (SI), and Serial Data Out (SO). All programming
cycles are completely self-timed and do not require an erase
before WRITE.
BLOCK WRITE protection is provided by programming the STA-
TUS REGISTER with one of four levels of write protection.
Additionally, separate WRITE enable and WRITE disable instruc-
tions are provided for data protection.
Features
s 2.1 MHz clock rate @ 2.7V to 5.5V
s 4096 bits organized as 512 x 8
s Multiple chips on the same 3-wire bus with separate chip
select lines
s Self-timed programming cycle
s Simultaneous programming of 1 to 4 bytes at a time
s Status register can be polled during programming to monitor
READY/BUSY
s Write Protect (WP) pin and write disable instruction for both
hardware and software write protection
s Block write protect feature to protect against accidental
writes
s Endurance: 1,000,000 data changes
s Data retention greater than 40 years
s Packages available: 8-pin DIP, 8-pin SO, or 8-pin TSSOP
Hardware data protection is provided by the WP pin to protect
against inadvertent programming. The HOLD pin allows the serial
communication to be suspended without resetting the serial
sequence.
Block Diagram
CS
Instruction
VCC
HOLD
Decoder
VSS
SCK
Control Logic
SI
Instruction
Register
and Clock
Generators
WP
Address
Counter/
Register
Decoder
1 of 512
Program
Enable
VPP
EEPROM Array
4096 Bits
(512 x 8)
High Voltage
Generator
and
Program
Timer
Read/Write Amps
Data In/Out Register
8 Bits
Data Out
Buffer
SO
Non-Volatile
Status Register
DS012401-1
© 1999 Fairchild Semiconductor Corporation
1
NM25C040 Rev. D.1
www.fairchildsemi.com
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