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NE5020N View Datasheet(PDF) - Philips Electronics

Part Name
Description
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NE5020N
Philips
Philips Electronics Philips
NE5020N Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Philips Semiconductors Linear Products
10-Bit µP-compatible D/A converter
Product specification
NE5020
TTL,
DTL VTH = +1.4V
NE5020
DIG GND (PIN 1)
VTH = VPIN1 + 1.4V
+15V CMOS, HTL, HNIL
VTH = +7.6V
+12V TO +15V
+15V
10k
9.1k
PIN 1
PIN 1
6.2V
ZENER
6.2k
0.1µF
+5V CMOS
VTH = +2.8V
+5V
3.6k
PIN 1
IN4148
+10V CMOS
VTH = +9.0V
+10V
6.2k
3.6k
PIN 1
0.1µF
PMOS
VTH = 0V
IN4148
PIN 1
10k
–5V TO –10V
NOTE: DO NOT EXCEED NEGATIVE
LOGIC INPUT RANGE OF DAC
10k ECL
VTH –1.29V
1.3k
3.9k
2N3904
IN4148
PIN 1
1k
Figure 10.
CIRCUIT DESCRIPTION
The NE5020 provides ten data latches, an internal voltage
reference, application resistors, and a scaled output voltage in
addition to the basic DAC components (see Block Diagram).
Latch Circuit
Digital interface with the NE5020 is readily accomplished through
the use of two latch enable ports (LE1 and LE2) and ten data input
latches. LE2 controls the two most significant bits of data (DB9 and
DB8) while LE1 controls the eight lesser significant bits (DB7 through
DB0). Both the latch enable ports (LE) and the data inputs are
static- and threshold-sensitive. When the latch enable ports (LE)
are high (Logic ‘1’) the data inputs become very high impedances
and essentially disappear from the data bus. Addressing the LE
with a low static (Logic ‘0’), the latches become active and adapt the
logic states present on the data bus. During this state, the output of
the DAC will change to the value proportional to the data bus value.
When the latch enable returns to a high state, the selected set of
data inputs (i.e., depending on which LE goes high) ‘memorizes’ the
data bus logic states and the output changes to the unique output
value corresponding to the binary word in the latch.
The data inputs are inactive and high impedance (typically requiring
–2µA for low (0.8V max) or 0.1µA for high (2.0V min) when the LE is
high. Any changes on the data bus with LE high will have no effect
on the DAC output.
The digital logic inputs (LE and DB) for the NE5020 utilize a
differential input logic system with a threshold level of +1.4V with
respect to the voltage level on the digital ground pin (Pin 1). Figure
10 details several bias schemes used to provide the proper
threshold voltage levels for various logic families.
To be compatible with a bus-oriented system, the DAC should
respond in as short a period as possible to insure full utilization of
the microprocessor, controller and I/O control lines. Figure 9 shows
the typical timing requirements of the latch and data lines. This
figure indicates that data on the data bus should be stable for at
least 50ns after LE is changed to a high state.
The independent LE (LE1 and LE2) lines allow for direct interface
from an 8-bit bus (see Figure 11). Data for the two MSBs is supplied
and stored when LE2 is activated low and returned high according to
the NE5020 timing requirements. Then LE1 is activated low and the
remaining eight LSBs of data are transferred into the DAC. With
LE1 returning high, the loading of 10-bit data word from an 8-bit data
bus is complete.
Occasionally the analog output must change to its data value within
one data address operation. This is no problem using the NE5020
on a 16-bit bus or any other data bus with 10 or greater data bits.
This can be accomplished from an 8-bit data bus by utilizing an
external latch circuit to pre-load the two MSB data values. Figure 12
shows the circuit configuration.
After pre-loading (via LE pre-load) the external latch with the two
MSB values, LE2 is activated low and the eight LSBs and the two
MSBs are concurrently loaded into the DAC in one address
operation. This permits the DAC output to make its appropriate
change at one time.
August 31, 1994
763
 

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