datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

NE1618DS View Datasheet(PDF) - Philips Electronics

Part Name
Description
View to exact match
NE1618DS Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Philips Semiconductors
Temperature monitor for microprocessor systems
Product data
NE1618
SMBus INTERFACE AC SPECIFICATIONS
VDD = 3.0 V to 3.6 V; Tamb = 0 °C to +125 °C unless otherwise noted.
These specifications are guaranteed by design and not tested in production.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ VIH
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ VIL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ IOL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ IIH & IIL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ fSCLK
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ tLOW
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ tHIGH
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ tBUF
Logic input high voltage for STBY, SCLK, SDATA
Logic input low voltage for STBY, SCLK, SDATA
Logic output low sink current for
ALERT
SDATA
Logic input current
SMBus input capacitance for SCLK, SDATA
SCLK operating frequency
SCLK low time
SCLK high time
SMBus free time.
Delay from SDA stop to SDA start
VDD = 3 V to 5.5 V
2.2
VDD = 3 V to 5.5 V
VOL = 0.4 V
1.0
VOL = 0.6 V
6.0
VIN = VDD or GND
–1.0
5
See Figure 4
0
See Figure 4
4.7
5.0
See Figure 4
4.0
5.0
See Figure 4
4.7
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ tHD:STA
Hold time of start condition.
Delay from SDA start to first SCL H–L
See Figure 4
4.0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ tHD:DAT
Hold time of data.
Delay from SCL H–L to SDA edges
See Figure 4
0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ tSU:DAT
set-up time of data.
Delay from SDA edges to SCL L–H
See Figure 4
250
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ tSU:STA
set-up time of repeat start condition.
Delay from SCL L–H to restart SDA
See Figure 4
250
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ tSU:STO
set-up time of stop condition.
Delay from SCL L–H to SDA stop.
See Figure 4
4.0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ tF
Fall time of SCL and SDA
See Figure 4
MAX
0.8
1.0
100
1.0
UNIT
V
V
mA
mA
µA
pF
kHz
µs
µs
µs
µs
ns
ns
ns
µs
µs
tLOW
tR
tF
tHD:STA
SCLK
tHD:STA
tHD:DAT
tHIGH
tSU:DAT
tSU:STA
tSU:STO
SDATA
tBUF
P
S
S
Figure 4. Timing measurements.
NOTE:
The NE1618 does not include the SMBus timeout capability (tLOW:SEXT and tLOW:MEXT).
P
SL01204
2002 Jan 04
6
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]