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NBSG16VSBA View Datasheet(PDF) - ON Semiconductor

Part NameDescriptionManufacturer
NBSG16VSBA 2.5V/3.3V SiGe Differential Receiver/Driver with Variable Output Swing ON-Semiconductor
ON Semiconductor ON-Semiconductor
NBSG16VSBA Datasheet PDF : 14 Pages
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NBSG16VS
Table 10. AC CHARACTERISTICS for QFN−16 VCC = 0 V; VEE = −3.465 V to −3.0 V or VCC = 3.0 V to 3.465 V; VEE = 0 V
−40°C
25°C
85°C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 8) (Note 34)
Min
Typ Max Min
Typ Max Min
Typ Max Unit
10
12
(Note 37)
10
12
(Note 37)
10
12
(Note 37)
GHz
tPLH,
Propagation Delay to
tPHL
Output Differential
(VCTRL = VCC − 2 V) D Q, Q
100
(VCTRL = VCC − 1 V) D Q, Q
100
tSKEW Duty Cycle Skew (Note 35)
tJITTER
RMS Random Clock Jitter
fin < 10 GHz
Peak−to−Peak Data Dependent Jitter
fin < 10 Gb/s
VINPP Input Voltage Swing/Sensitivity
75
(Differential Configuration) (Note 36)
140 180 100
135 180 100
3 20
0.5 2
TBD
2600
75
140 180
100
135 180
80
3 15
0.5 2
TBD
2600 75
ps
140 180
135 220
3 10 ps
ps
0.5 2
TBD
2600 mV
tr
Output Rise/Fall Times (20% − 80%)
ps
tf
@ 1 GHz
(VCTRL = VCC − 2 V) Q, Q
30
45 55
30
45 55
30
45 55
(VCTRL = VCC − 1 V) Q, Q
30
40 50
30
40 50
30
40 50
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
34. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC−2.0 V. Input edge rates 40 ps (20% − 80%).
35. tSKEW = |tPLH−tPHL| for a nominal 50% differential clock input waveform. See Figure 10.
36. VINPP(MAX) cannot exceed VCC − VEE (applicable only when VCC − VEE t 2600 mV).
37. Conditions include input amplitude of 500 mV and VCTRL = VCC − 2 V. Minimum output amplitude guarantee of 100 mV (see Output P−P
Spec in Figure 8).
Table 11. AC CHARACTERISTICS for QFN−16 VCC = 0 V; −3.0 V tVEE v −2.375 V or 2.375 V v VCC t 3.0 V; VEE = 0 V
−40°C
25°C
85°C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 9) (Note 38)
Min
Typ Max Min
Typ Max Min
Typ Max Unit
10
12
(Note 41)
10
12
(Note 41)
10
12
(Note 41)
GHz
tPLH,
Propagation Delay to
tPHL
Output Differential
(VCTRL = VCC − 2 V) D Q, Q
100
(VCTRL = VCC − 1 V) D Q, Q
100
tSKEW Duty Cycle Skew (Note 39)
tJITTER
RMS Random Clock Jitter
fin < 10 GHz
Peak−to−Peak Data Dependent Jitter
fin < 10 Gb/s
VINPP Input Voltage Swing/Sensitivity
75
(Differential Configuration) (Note 40)
140 180
100
135 180
100
3 20
0.5 3
TBD
2600 75
140 180
80
135 180 100
3 15
0.5 3
TBD
2600
75
ps
140 180
135 220
3 10 ps
ps
0.5 3
TBD
2600 mV
tr
Output Rise/Fall Times (20% − 80%)
ps
tf
@ 1 GHz
(VCTRL = VCC − 2 V) Q, Q
25
50 70
25
50 70
25
50 70
(VCTRL = VCC − 1 V) Q, Q
22
45 60
22
45 60
22
45 60
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
38. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC−2.0 V. Input edge rates 40 ps (20% − 80%).
39. tSKEW = |tPLH−tPHL| for a nominal 50% differential clock input waveform. See Figure 10.
40. VINPP(MAX) cannot exceed VCC − VEE (applicable only when VCC − VEE t 2600 mV).
41. Conditions include input amplitude of 500 mV and VCTRL = VCC − 2 V. Minimum output amplitude guarantee of 100 mV (see Output P−P
Spec in Figure 9).
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