NBSG16VSMNR2G View Datasheet(PDF) - ON Semiconductor
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NBSG16VSMNR2G Datasheet PDF : 14 Pages
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NBSG16VS
Table 8. AC CHARACTERISTICS for FCBGA−16 VCC = 0 V; VEE = −3.465 V to −3.0 V or VCC = 3.0 V to 3.465 V; VEE = 0 V
−40°C
25°C
85°C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 8) (Note 26)
Min Typ
10.7
12
(Note 29)
Max Min Typ
10.7
12
(Note 29)
Max Min Typ
10.7
12
(Note 29)
Max Unit
GHz
tPLH,
tPHL
Propagation Delay to Output Differen-
tial
(VCTRL = VCC − 2 V) D → Q, Q
(VCTRL = VCC − 1 V) D → Q, Q
ps
100
125 145
100
125 145
100
125 145
100
120 140
100
120 140
100
120 140
tSKEW Duty Cycle Skew (Note 27)
3 10
3 10
3 10 ps
tJITTER
RMS Random Clock Jitter
fin < 10 GHz
Peak−to−Peak Data Dependent Jitter
fin < 10 Gb/s
0.8 2
TBD
0.8 2
TBD
ps
0.8 2
TBD
VINPP Input Voltage Swing/Sensitivity
75
(Differential Configuration) (Note 28)
2600 75
2600
75
2600 mV
tr
Output Rise/Fall Times (20% − 80%)
ps
tf
@ 1 GHz
(VCTRL = VCC − 2 V) Q, Q
30
45 55
30
45 55
30
45 55
(VCTRL = VCC − 1 V) Q, Q
30
40 50
30
40 50
30
40 50
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
26. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC−2.0 V. Input edge rates 40 ps (20% − 80%).
27. tSKEW = |tPLH−tPHL| for a nominal 50% differential clock input waveform. See Figure 10.
28. VINPP(MAX) cannot exceed VCC − VEE (applicable only when VCC − VEE t 2600 mV).
29. Conditions include input amplitude of 500 mV and VCTRL = VCC − 2 V. Minimum output amplitude guarantee of 100 mV (see Output P−P
Spec in Figure 8).
Table 9. AC CHARACTERISTICS for FCBGA−16 VCC = 0 V; −3.0 V tVEE v −2.375 V or 2.375 V v VCC t 3.0 V; VEE = 0 V
−40°C
25°C
85°C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 9) (Note 30)
Min
Typ Max Min
Typ Max Min
Typ Max Unit
10.7
12
(Note 33)
10.7
12
(Note 33)
10.7
12
(Note 33)
GHz
tPLH,
Propagation Delay to Output Differen-
tPHL
tial
(VCTRL = VCC − 2 V) D → Q, Q
100
(VCTRL = VCC − 1 V) D → Q, Q
100
tSKEW Duty Cycle Skew (Note 31)
tJITTER
RMS Random Clock Jitter
fin < 10 GHz
Peak−to−Peak Data Dependent Jitter
fin < 10 Gb/s
VINPP Input Voltage Swing/Sensitivity
75
(Differential Configuration) (Note 32)
125 145
100
120 140
100
3 10
0.9 3
TBD
2600 75
125 145 100
120 140 100
3 10
0.9 3
TBD
2600
75
ps
125 145
120 140
3 10 ps
ps
0.9 3
TBD
2600 mV
tr
Output Rise/Fall Times (20% − 80%)
ps
tf
@ 1 GHz
(VCTRL = VCC − 2 V) Q, Q
25
50 70
25
50 70
25
50 70
(VCTRL = VCC − 1 V) Q, Q
22
45 60
22
45 60
22
45 60
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
30. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC−2.0 V. Input edge rates 40 ps (20% − 80%).
31. tSKEW = |tPLH−tPHL| for a nominal 50% differential clock input waveform. See Figure 10.
32. VINPP(MAX) cannot exceed VCC − VEE (applicable only when VCC − VEE t 2600 mV).
33. Conditions include input amplitude of 500 mV and VCTRL = VCC − 2 V. Minimum output amplitude guarantee of 100 mV (see Output P−P
Spec in Figure 9).
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