NBSG16VSMNR2G View Datasheet(PDF) - ON Semiconductor
Part Name
Description
View to exact match
NBSG16VSMNR2G Datasheet PDF : 14 Pages
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1
A
VEE
2
3
4
NC
VCTRL
VEE
B
D
VTD
VCC
Q
C
D
VTD
VCC
Q
D
VEE
VBB
VMM
VEE
Figure 1. BGA−16 Pinout (Top View)
NBSG16VS
VEE VBB VMM VEE
16 15 14 13
Exposed Pad (EP)
VTD 1
D2
D3
VTD 4
NBSG16VS
12 VCC
11 Q
10 Q
9 VCC
5678
VEE NC VCTRL VEE
Figure 2. QFN−16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
BGA
C2
QFN
1
Name
VTD
I/O
Description
−
Internal 50 W Termination Pin. See Table 2.
C1
2
D
ECL, CML, Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to VCC.
LVCMOS,
LVDS,
LVTTL
Input
B1
3
D
ECL, CML, Noninverted Differential Input. Internal 75 kW to VEE.
LVCMOS,
LVDS,
LVTTL
Input
B2
4
VTD
−
Internal 50 W Termination Pin. See Table 2.
A1,D1,A4, 5,8,13,16
VEE
D4
−
Negative Supply Voltage
A2
6
NC
−
No Connect
A3
B3,C3
B4
C4
7
9,12
10
11
VCTRL
VCC
Q
Q
−
RSECL
Output
RSECL
Output
Output Amplitude Swing Control. Bypass Pin to VCC through 0.1 mF Capacitor.
Positive Supply Voltage
Noninverted Differential Output. Typically Terminated with 50 W to
VTT = VCC − 2 V
Inverted Differential Output. Typically Terminated with 50 W to VTT = VCC − 2 V
D3
14
VMM
−
LVCMOS Reference Voltage Output. (VCC − VEE)/2
D2
15
VBB
−
ECL Reference Voltage Output
N/A
−
EP
−
Exposed Pad. (Note 2)
1. The NC pin is electrically connected to the die and must be left open.
2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package
bottom (see case drawing) must be attached to a heat−sinking conduit.
3. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage, and if no signal
is applied then the device will be susceptible to self−oscillation.
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