NBSG16MNR2G View Datasheet(PDF) - ON Semiconductor
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NBSG16MNR2G Datasheet PDF : 12 Pages
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NBSG16
Table 8. AC CHARACTERISTICS for FCBGA−16
VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
−40°C
25°C
85°C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 4. Fmax/JITTER) (Note 17)
tPLH,
tPHL
Propagation Delay to
Output Differential
tSKEW Duty Cycle Skew (Note 18)
tJITTER
RMS Random Clock Jitter
fin < 10 GHz
Peak−to−Peak Data Dependent Jitter
fin < 10 Gb/s
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 19)
Min
10.7
90
75
Typ Max Min
12
10.7
110 130 100
3 15
0.2 1
TBD
2600 75
Typ Max
12
120 140
3
15
0.2
1
TBD
2600
Min
10.7
105
75
Typ Max Unit
12
GHz
125 145 ps
3
15 ps
ps
0.2
1
TBD
2600 mV
tr
Output Rise/Fall Times @ 1 GHz Q, Q 30
45 75
20
40 65
20
40 65 ps
tf
(20% − 80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
17. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. Input edge rates 40 ps (20% − 80%).
18. See Figure 6. tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform.
19. VINPP(max) cannot exceed VCC − VEE
Table 9. AC CHARACTERISTICS for QFN−16
VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
−40°C
25°C
85°C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 4. Fmax/JITTER) (Note 20)
tPLH,
tPHL
Propagation Delay to
Output Differential
Min Typ Max Min Typ Max Min Typ Max Unit
10.7 12
10.7 12
10.7 12
GHz
90 110 130 100 120 140 95 125 145 ps
tSKEW Duty Cycle Skew (Note 21)
3 15
3
15
3
15 ps
tJITTER
RMS Random Clock Jitter
fin < 10 GHz
Peak−to−Peak Data Dependent Jitter
fin < 10 Gb/s
0.2 2
TBD
0.2
2
TBD
ps
0.2
2
TBD
VINPP Input Voltage Swing/Sensitivity
75
(Differential Configuration) (Note 22)
2600 75
2600 75
2600 mV
tr
Output Rise/Fall Times @ 1 GHz Q, Q 20
30 50
20
30 50
20
30 50 ps
tf
(20% − 80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. Input edge rates 40 ps (20% − 80%).
21. See Figure 6. tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform.
22. VINPP(max) cannot exceed VCC − VEE
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