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NB3N5573DTR2G View Datasheet(PDF) - ON Semiconductor

Part Name
Description
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NB3N5573DTR2G
ON-Semiconductor
ON Semiconductor ON-Semiconductor
NB3N5573DTR2G Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
NB3N5573
Table 6. AC CHARACTERISTICS (VDD = 3.3 V ±10%, GND = 0 V, TA = -40°C to +85°C; Note 5)
Symbol
Characteristic
Min
fCLKIN
fCLKOUT
WNOISE
Clock/Crystal Input Frequency
Output Clock Frequency
Phase-Noise Performance
25
fCLKout = 200 MHz
@ 100 Hz offset from carrier
@ 1 kHz offset from carrier
@ 10 kHz offset from carrier
@ 100 kHz offset from carrier
@ 1 MHz offset from carrier
@ 10 MHz offset from carrier
Tjitter
OE
Period Jitter Peak-to-Peak (Note 6)
Period Jitter RMS (Note 6)
Cycle-Cycle RMS Jiter (Note 7)
Cycle-to-Cycle Peak to Peak Jitter (Note 7)
Output Enable/Disable Time
fCLKout = 200 MHz
fCLKout = 200 MHz
fCLKout = 200 MHz
fCLKout = 200 MHz
tDUTY_CYCLE Output Clock Duty Cycle (Measured at cross point)
45
tR
Output Risetime (Measured from 175 mV to 525 mV, Figure 4)
175
tF
Output Falltime (Measured from 525 mV to 175 mV, Figure 4)
175
DtR
Output Risetime Variation (Single-Ended)
DtF
Output Falltime Variation (Single-Ended)
Stabilization Stabilization Time From Powerup VDD = 3.3 V
Time
Typ
25
-103
-1 18
-122
-130
-132
-149
10
1.5
2
20
50
340
340
3.0
Max
Unit
MHz
200
MHz
dBc/Hz
20
ps
3
5
35
ps
1
ms
55
%
700
ps
700
ps
125
ps
125
ps
ms
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Measurement taken from differential output on single-ended channel terminated with RS = 33.2 W, RL = 49.9 W, with test load capacitance
of 2 pF and current biasing resistor set at 475 W. See Figure 3.
6. Sampled with 10000 cycles.
7. Sampled with 1000 cycles.
CLK0
CLK0
RL = 33.2 W
RL = 33.2 W
HCSL
Driver
CLK1
RL = 33.2 W
RL = 33.2 W
CLK2
Zo = 50 W
Zo = 50 W
Zo = 50 W
Zo = 50 W
RL = 49.9 W
RL =
49.9 W
Receiver
RL = 49.9 W
RL =
49.9 W
Figure 3. Typical Termination for Output Driver and Device Evaluation
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