NB3N551 View Datasheet(PDF) - ON Semiconductor

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NB3N551

3.3 V / 5.0 V Ultra-Low Skew 1:4 Clock Fanout Buffer

ON Semiconductor 

NB3N551

Figure 2. Phase Noise Plot at 25 MHz at an Operating Voltage of 3.3 V, Room Temperature

The above plot captured using Agilent E5052A shows Additive Phase Noise of the NB3N551 device measured with an input

source generated by Agilent E8663B. The RMS phase jitter contributed by the device (integrated between 12 kHz to 20 MHz;

as shown in the shaded region of the plot) is 43 fs (RMS Jitter of the input source is 203.31 fs and Output (DUT+Source) is

247.06 fs).

Figure 3. Phase Noise Plot at 50 MHz at an Operating Voltage of 5 V, Room Temperature

The above plot captured using Agilent E5052A shows Additive Phase Noise of the NB3N551 device measured with an input

source generated by Agilent E8663B. The RMS phase jitter contributed by the device (integrated between 12 kHz to 20 MHz;

as shown in the shaded region of the plot) is 16 fs (RMS Jitter of the input source is 104.08 fs and Output (DUT + Source) is

119.77 fs).

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